SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
                *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
                return 0;
+       case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
+               ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
+               if (!ret)
+                       *size = 8;
+               break;
        default:
                ret = -EINVAL;
                break;
 
                        msg, feature_mask);
 }
 
-static int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
-               uint32_t *features_enabled)
+int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
+                           uint64_t *features_enabled)
 {
        if (features_enabled == NULL)
                return -EINVAL;
 
 static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
 {
-       uint32_t features_enabled = 0;
+       uint64_t features_enabled = 0;
 
-       vega10_get_smc_features(hwmgr, &features_enabled);
+       vega10_get_enabled_smc_features(hwmgr, &features_enabled);
 
        if (features_enabled & SMC_DPM_FEATURES)
                return true;
 
 
 int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
                               bool enable, uint32_t feature_mask);
+int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
+                                   uint64_t *features_enabled);
 
 #endif