RISC-V: hwprobe: Add SCALAR to misaligned perf defines

In preparation for misaligned vector performance hwprobe keys, rename
the hwprobe key values associated with misaligned scalar accesses to
include the term SCALAR. Leave the old defines in place to maintain
source compatibility.

This change is intended to be a functional no-op.

Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240809214444.3257596-3-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index a994eed75bde0380830f6818b7aebc3da96c9f51..85b709257918ade7590ebbf2f0f53dcdf8ed36be 100644 (file)
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -247,23 +247,25 @@ The following keys are defined:
   the performance of misaligned scalar native word accesses on the selected set
   of processors.
 
-  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned
-    accesses is unknown.
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of
+    misaligned scalar accesses is unknown.
 
-  * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are
-    emulated via software, either in or below the kernel.  These accesses are
-    always extremely slow.
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar
+    accesses are emulated via software, either in or below the kernel.  These
+    accesses are always extremely slow.
 
-  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned native word
-    sized accesses are slower than the equivalent quantity of byte accesses.
-    Misaligned accesses may be supported directly in hardware, or trapped and
-    emulated by software.
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native
+    word sized accesses are slower than the equivalent quantity of byte
+    accesses. Misaligned accesses may be supported directly in hardware, or
+    trapped and emulated by software.
 
-  * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned native word
-    sized accesses are faster than the equivalent quantity of byte accesses.
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native
+    word sized accesses are faster than the equivalent quantity of byte
+    accesses.
 
-  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
-    not supported at all and will generate a misaligned address fault.
+  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar
+    accesses are not supported at all and will generate a misaligned address
+    fault.
 
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicboz block in bytes.

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 6357530842752af49c37afa4dc454dd5e6f2ce96..1e153cda57db85b99d40f4fcc67aa69651a0f856 100644 (file)
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -83,6 +83,11 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7
 #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ        8
 #define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF       9
+#define                RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN         0
+#define                RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED        1
+#define                RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW            2
+#define                RISCV_HWPROBE_MISALIGNED_SCALAR_FAST            3
+#define                RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED     4
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 2d0f4f6a32c3fcc130ea09186d09910089bfe294..cea0ca2bf2a25ecc671e31b141e84c6d1977da25 100644 (file)
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -178,13 +178,13 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus)
                        perf = this_perf;
 
                if (perf != this_perf) {
-                       perf = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
+                       perf = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;
                        break;
                }
        }
 
        if (perf == -1ULL)
-               return RISCV_HWPROBE_MISALIGNED_UNKNOWN;
+               return RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;
 
        return perf;
 }
@@ -192,12 +192,12 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus)
 static u64 hwprobe_misaligned(const struct cpumask *cpus)
 {
        if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS))
-               return RISCV_HWPROBE_MISALIGNED_FAST;
+               return RISCV_HWPROBE_MISALIGNED_SCALAR_FAST;
 
        if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_available())
-               return RISCV_HWPROBE_MISALIGNED_EMULATED;
+               return RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED;
 
-       return RISCV_HWPROBE_MISALIGNED_SLOW;
+       return RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW;
 }
 #endif
 

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index b62d5a2f4541e754cc7ea322e38d42b4dab65b90..192cd5603e95f9b92211cb616b98df7c6bc602d9 100644 (file)
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -338,7 +338,7 @@ int handle_misaligned_load(struct pt_regs *regs)
        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
 
 #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
-       *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED;
+       *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED;
 #endif
 
        if (!unaligned_enabled)
@@ -532,13 +532,13 @@ static bool check_unaligned_access_emulated(int cpu)
        unsigned long tmp_var, tmp_val;
        bool misaligned_emu_detected;
 
-       *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
+       *mas_ptr = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN;
 
        __asm__ __volatile__ (
                "       "REG_L" %[tmp], 1(%[ptr])\n"
                : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory");
 
-       misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED);
+       misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED);
        /*
         * If unaligned_ctl is already set, this means that we detected that all
         * CPUS uses emulated misaligned access at boot time. If that changed

diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
index a9a6bcb02acf111cee35a274716a1c78cbdf5886..160628a2116de4a5e4135e4bba25fef35141b747 100644 (file)
--- a/arch/riscv/kernel/unaligned_access_speed.c
+++ b/arch/riscv/kernel/unaligned_access_speed.c
@@ -34,9 +34,9 @@ static int check_unaligned_access(void *param)
        struct page *page = param;
        void *dst;
        void *src;
-       long speed = RISCV_HWPROBE_MISALIGNED_SLOW;
+       long speed = RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW;
 
-       if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN)
+       if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN)
                return 0;
 
        /* Make an unaligned destination buffer. */
@@ -95,14 +95,14 @@ static int check_unaligned_access(void *param)
        }
 
        if (word_cycles < byte_cycles)
-               speed = RISCV_HWPROBE_MISALIGNED_FAST;
+               speed = RISCV_HWPROBE_MISALIGNED_SCALAR_FAST;
 
        ratio = div_u64((byte_cycles * 100), word_cycles);
        pr_info("cpu%d: Ratio of byte access time to unaligned word access is %d.%02d, unaligned accesses are %s\n",
                cpu,
                ratio / 100,
                ratio % 100,
-               (speed == RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow");
+               (speed == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST) ? "fast" : "slow");
 
        per_cpu(misaligned_access_speed, cpu) = speed;
 
@@ -110,7 +110,7 @@ static int check_unaligned_access(void *param)
         * Set the value of fast_misaligned_access of a CPU. These operations
         * are atomic to avoid race conditions.
         */
-       if (speed == RISCV_HWPROBE_MISALIGNED_FAST)
+       if (speed == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST)
                cpumask_set_cpu(cpu, &fast_misaligned_access);
        else
                cpumask_clear_cpu(cpu, &fast_misaligned_access);
@@ -188,7 +188,7 @@ static int riscv_online_cpu(unsigned int cpu)
        static struct page *buf;
 
        /* We are already set since the last check */
-       if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN)
+       if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN)
                goto exit;
 
        buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER);