arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region

This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.

Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-j7200-evm-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250402113201.151195-4-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
index 3cc315a0e0844d632d463ca314fe382d0d042903..281076d905f346b068d2fc978f1e328f5b3d50f6 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
@@ -48,6 +48,6 @@
                dma-coherent;
                phys = <&serdes0_pcie_link>;
                phy-names = "pcie-phy";
-               ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+               ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
        };
 };

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 5ab510a0605fd43b8b9bc0b2128d17f2afd0e4f1..dbb0006573774ac967c20ffe745cca3c3b4af1e4 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -32,6 +32,11 @@
                #size-cells = <1>;
                ranges = <0x00 0x00 0x00100000 0x1c000>;
 
+               pcie1_ctrl: pcie-ctrl@4074 {
+                       compatible = "ti,j784s4-pcie-ctrl", "syscon";
+                       reg = <0x4074 0x4>;
+               };
+
                serdes_ln_ctrl: mux-controller@4080 {
                        compatible = "reg-mux";
                        reg = <0x4080 0x20>;
@@ -764,7 +769,7 @@
                interrupt-names = "link_state";
                interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
                device_type = "pci";
-               ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+               ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
                max-link-speed = <3>;
                num-lanes = <4>;
                power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;