pr_info("mmio virtual addr = %p\n", sm750_dev->pvReg);
        }
 
-
        sm750_dev->accel.dprBase = sm750_dev->pvReg + DE_BASE_ADDR_TYPE1;
        sm750_dev->accel.dpPortBase = sm750_dev->pvReg + DE_PORT_ADDR_TYPE1;
 
        return ret;
 }
 
-
-
 int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
 {
        struct init_status *parm;
        if (parm->mem_clk == 0)
                parm->mem_clk = parm->chip_clk;
        if (parm->master_clk == 0)
-               parm->master_clk = parm->chip_clk/3;
+               parm->master_clk = parm->chip_clk / 3;
 
        ddk750_initHw((initchip_param_t *)&sm750_dev->initParm);
        /* for sm718,open pci burst */
        dispSet = 0;
        channel = *output->channel;
 
-
        if (getChipType() != SM750LE) {
                if (channel == sm750_primary) {
                        pr_info("primary channel\n");
                                dispSet |= do_LCD1_SEC;
                        if (output->paths & sm750_crt)
                                dispSet |= do_CRT_SEC;
-
                }
                ddk750_setLogicalDispOut(dispSet);
        } else {
                break;
        default:
                return -EINVAL;
-
        }
 
        return 0;
 }
 
-
 /*
        set the controller's mode for @crtc charged with @var and @fix parameters
 */
        struct sm750_dev *sm750_dev;
        struct lynxfb_par *par;
 
-
        ret = 0;
        par = container_of(crtc, struct lynxfb_par, crtc);
        sm750_dev = par->dev;
 
        /* set timing */
        modparm.pixel_clock = ps_to_hz(var->pixclock);
-       modparm.vertical_sync_polarity = (var->sync & FB_SYNC_HOR_HIGH_ACT) ? POS:NEG;
-       modparm.horizontal_sync_polarity = (var->sync & FB_SYNC_VERT_HIGH_ACT) ? POS:NEG;
-       modparm.clock_phase_polarity = (var->sync & FB_SYNC_COMP_HIGH_ACT) ? POS:NEG;
+       modparm.vertical_sync_polarity = (var->sync & FB_SYNC_HOR_HIGH_ACT)
+                                        ? POS : NEG;
+       modparm.horizontal_sync_polarity = (var->sync & FB_SYNC_VERT_HIGH_ACT)
+                                          ? POS : NEG;
+       modparm.clock_phase_polarity = (var->sync & FB_SYNC_COMP_HIGH_ACT)
+                                      ? POS : NEG;
        modparm.horizontal_display_end = var->xres;
        modparm.horizontal_sync_width = var->hsync_len;
        modparm.horizontal_sync_start = var->xres + var->right_margin;
                reg |= ((var->bits_per_pixel >> 4) &
                        CRT_DISPLAY_CTRL_FORMAT_MASK);
                POKE32(CRT_DISPLAY_CTRL, reg);
-
        }
 
-
 exit:
        return ret;
 }
 {
        static unsigned int add[] = {PANEL_PALETTE_RAM, CRT_PALETTE_RAM};
 
-       POKE32(add[crtc->channel] + index*4, (red<<16)|(green<<8)|blue);
+       POKE32(add[crtc->channel] + index * 4,
+              (red << 16) | (green << 8) | blue);
        return 0;
 }
 
        return 0;
 }
 
-
 void hw_sm750_initAccel(struct sm750_dev *sm750_dev)
 {
        u32 reg;
        return -1;
 }
 
-
 int hw_sm750_deWait(void)
 {
        int i = 0x10000000;