net/mlx5: Add FPGA QP error event

The FPGA queue pair (QP) event fires whenever a QP on the FPGA
transitions to the error state.

At this stage, this event is unrecoverable, it may become recoverable
in the future.

Signed-off-by: Ilan Tayari <ilant@mellanox.com>
Signed-off-by: Adi Nissim <adin@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
index 1a3a2b9a723245ad04c3fdf085863b39be3a3720..406c23862f5f76557f84aa83144e6119521522e3 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
@@ -164,6 +164,8 @@ static const char *eqe_type_str(u8 type)
                return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
        case MLX5_EVENT_TYPE_FPGA_ERROR:
                return "MLX5_EVENT_TYPE_FPGA_ERROR";
+       case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
+               return "MLX5_EVENT_TYPE_FPGA_QP_ERROR";
        case MLX5_EVENT_TYPE_GENERAL_EVENT:
                return "MLX5_EVENT_TYPE_GENERAL_EVENT";
        default:
@@ -563,6 +565,7 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
                        break;
 
                case MLX5_EVENT_TYPE_FPGA_ERROR:
+               case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
                        mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
                        break;
 
@@ -842,11 +845,11 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
                async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
 
        if (MLX5_CAP_GEN(dev, fpga))
-               async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);
+               async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |
+                                   (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);
        if (MLX5_CAP_GEN_MAX(dev, dct))
                async_event_mask |= (1ull << MLX5_EVENT_TYPE_DCT_DRAINED);
 
-
        if (MLX5_CAP_GEN(dev, temp_warn_event))
                async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
 

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index c1095e08f0c8848c74a5248383cb83465f3ef7ed..0f006cf8343df0d234408e34d8014fabb318bb0c 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -331,6 +331,7 @@ enum mlx5_event {
        MLX5_EVENT_TYPE_DCT_DRAINED        = 0x1c,
 
        MLX5_EVENT_TYPE_FPGA_ERROR         = 0x20,
+       MLX5_EVENT_TYPE_FPGA_QP_ERROR      = 0x21,
 };
 
 enum {

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index ca6c0dfb5ffe5f2afbda7c9565f0fe582399ac83..8e0b8865f91e1e9b02ea16718119488d2b95b63a 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -60,6 +60,7 @@ enum {
        MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
        MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
        MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
+       MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
 };
 
 enum {

diff --git a/include/linux/mlx5/mlx5_ifc_fpga.h b/include/linux/mlx5/mlx5_ifc_fpga.h
index 193091537cb6da1968b016b21d9f62b68da4b605..64d0f40d4cc36924ff051bfa14db27fe56a8af89 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc_fpga.h
+++ b/include/linux/mlx5/mlx5_ifc_fpga.h
@@ -470,6 +470,22 @@ struct mlx5_ifc_ipsec_counters_bits {
        u8         dropped_cmd[0x40];
 };
 
+enum {
+       MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED  = 0x1,
+       MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED            = 0x2,
+};
+
+struct mlx5_ifc_fpga_qp_error_event_bits {
+       u8         reserved_at_0[0x40];
+
+       u8         reserved_at_40[0x18];
+       u8         syndrome[0x8];
+
+       u8         reserved_at_60[0x60];
+
+       u8         reserved_at_c0[0x8];
+       u8         fpga_qpn[0x18];
+};
 enum mlx5_ifc_fpga_ipsec_response_syndrome {
        MLX5_FPGA_IPSEC_RESPONSE_SUCCESS = 0,
        MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1,