return IRQ_HANDLED;
 }
 
-static void imx_disable_rx_int(struct imx_port *sport)
-{
-       unsigned long temp;
-
-       /* disable the receiver ready and aging timer interrupts */
-       temp = readl(sport->port.membase + UCR1);
-       temp &= ~(UCR1_RRDYEN);
-       writel(temp, sport->port.membase + UCR1);
-
-       temp = readl(sport->port.membase + UCR2);
-       temp &= ~(UCR2_ATEN);
-       writel(temp, sport->port.membase + UCR2);
-
-       /* disable the rx errors interrupts */
-       temp = readl(sport->port.membase + UCR4);
-       temp &= ~UCR4_OREN;
-       writel(temp, sport->port.membase + UCR4);
-}
-
 static void clear_rx_errors(struct imx_port *sport);
 
 /*
        if (sport->dma_is_inited && !sport->dma_is_enabled)
                imx_enable_dma(sport);
 
-       temp = readl(sport->port.membase + UCR1);
-       temp |= UCR1_RRDYEN | UCR1_UARTEN;
+       temp = readl(sport->port.membase + UCR1) & ~UCR1_RRDYEN;
+       if (!sport->dma_is_enabled)
+               temp |= UCR1_RRDYEN;
+       temp |= UCR1_UARTEN;
        if (sport->have_rtscts)
                        temp |= UCR1_RTSDEN;
 
        writel(temp, sport->port.membase + UCR1);
 
-       temp = readl(sport->port.membase + UCR4);
-       temp |= UCR4_OREN;
+       temp = readl(sport->port.membase + UCR4) & ~UCR4_OREN;
+       if (!sport->dma_is_enabled)
+               temp |= UCR4_OREN;
        writel(temp, sport->port.membase + UCR4);
 
-       temp = readl(sport->port.membase + UCR2);
+       temp = readl(sport->port.membase + UCR2) & ~UCR2_ATEN;
        temp |= (UCR2_RXEN | UCR2_TXEN);
        if (!sport->have_rtscts)
                temp |= UCR2_IRTS;
         * In our iMX53 the average delay for the first reception dropped from
         * approximately 35000 microseconds to 1000 microseconds.
         */
-       if (sport->dma_is_enabled) {
-               imx_disable_rx_int(sport);
+       if (sport->dma_is_enabled)
                start_rx_dma(sport);
-       }
 
        spin_unlock_irqrestore(&sport->port.lock, flags);