size_t bsz;
size_t config_cycle_count = sizeof(struct psif_epsc_csr_config)/sizeof(u32);
bool restarted_reset = false;
+ ulong cpu_eqs;
/* Max mailbox exchange protocol version supported by this driver */
u16 mailbox_seq_version_to_use = 2;
if (sif_cq_eq_max < 1)
sif_cq_eq_max = 1; /* Adjust - need at least 1 completion event queue */
- /* We only allocate resources for these */
- es->eqs.cnt = min_t(ulong, es->eqs.max_cnt, sif_cq_eq_max + 2);
+ /* Limit the number of eqs we allocate resources for to the
+ * cq_eq_max module parameter setting and the number of CPUs in the system:
+ */
+ cpu_eqs = min_t(ulong, sif_cq_eq_max, num_present_cpus());
+ es->eqs.cnt = min_t(ulong, es->eqs.max_cnt, cpu_eqs + 2);
ret = sif_eps_api_version_ok(sdev, eps_num);
if (ret)
MODULE_PARM_DESC(ki_spqp_size, "Number of privileged QPs for key invalidate stencils to set up");
/* pqp_size == cq_eq_max */
-uint sif_cq_eq_max = 12;
+uint sif_cq_eq_max = 46;
module_param_named(cq_eq_max, sif_cq_eq_max, uint, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(cq_eq_max, "Upper limit on no. of EQs to distribute completion events among");