KVM: arm64: Fix the value of the CPTR_EL2 RES1 bitmask for nVHE

Since the introduction of SME, bit 12 in CPTR_EL2 (nVHE) is TSM
for trapping SME, instead of RES1, as per ARM ARM DDI 0487K.a,
section D23.2.34.

Fix the value of CPTR_NVHE_EL2_RES1 to reflect that, and adjust
the code that relies on it accordingly.

Signed-off-by: Fuad Tabba <tabba@google.com>
Link: https://lore.kernel.org/r/20241216105057.579031-15-tabba@google.com
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 3e0f0de1d2da86ed84177a3c6732697015875b60..24e4ac7c50f2c43b74abd01a44b5e7c94d06afa2 100644 (file)
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -300,7 +300,7 @@
 #define CPTR_EL2_TSM   (1 << 12)
 #define CPTR_EL2_TFP   (1 << CPTR_EL2_TFP_SHIFT)
 #define CPTR_EL2_TZ    (1 << 8)
-#define CPTR_NVHE_EL2_RES1     0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */
+#define CPTR_NVHE_EL2_RES1     (BIT(13) | BIT(9) | GENMASK(7, 0))
 #define CPTR_NVHE_EL2_RES0     (GENMASK(63, 32) |      \
                                 GENMASK(29, 21) |      \
                                 GENMASK(19, 14) |      \

diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index 7b3dc52248ce475e5724fd1309e377523ad51f55..6602a4c091ac2131c7fb9961f3f6b7bda69afb6c 100644 (file)
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -640,8 +640,8 @@ static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu)
 
                if (vcpu_has_sve(vcpu) && guest_owns_fp_regs())
                        val |= CPTR_EL2_TZ;
-               if (cpus_have_final_cap(ARM64_SME))
-                       val &= ~CPTR_EL2_TSM;
+               if (!cpus_have_final_cap(ARM64_SME))
+                       val |= CPTR_EL2_TSM;
        }
 
        kvm_write_cptr_el2(val);