drm/i915: Regroup pipe CRC regs

Put all the definitions related to a single pipe CRC register
in one place, instead of the current approach where things are
spread all over the place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
index 66520c97bf1eae6e4424a62f15d1a607614af27a..a1217a4d6f2ef66af3d4312dc6960d0a453ba8cb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
@@ -8,8 +8,8 @@
 
 #include "intel_display_reg_defs.h"
 
-/* Pipe A CRC regs */
 #define _PIPE_CRC_CTL_A                        0x60050
+#define PIPE_CRC_CTL(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
 #define   PIPE_CRC_ENABLE              REG_BIT(31)
 /* skl+ source selection */
 #define   PIPE_CRC_SOURCE_MASK_SKL     REG_GENMASK(30, 28)
@@ -57,36 +57,39 @@
 /* gen2 doesn't have source selection bits */
 #define   PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
 
-#define _PIPE_CRC_RES_1_A_IVB          0x60064
-#define _PIPE_CRC_RES_2_A_IVB          0x60068
-#define _PIPE_CRC_RES_3_A_IVB          0x6006c
-#define _PIPE_CRC_RES_4_A_IVB          0x60070
-#define _PIPE_CRC_RES_5_A_IVB          0x60074
-
 #define _PIPE_CRC_RES_RED_A            0x60060
+#define PIPE_CRC_RES_RED(dev_priv, pipe)       _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
+
 #define _PIPE_CRC_RES_GREEN_A          0x60064
+#define PIPE_CRC_RES_GREEN(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
+
 #define _PIPE_CRC_RES_BLUE_A           0x60068
+#define PIPE_CRC_RES_BLUE(dev_priv, pipe)      _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
+
 #define _PIPE_CRC_RES_RES1_A_I915      0x6006c
+#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
+
 #define _PIPE_CRC_RES_RES2_A_G4X       0x60080
+#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)  _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
 
-/* Pipe B CRC regs */
+#define _PIPE_CRC_RES_1_A_IVB          0x60064
 #define _PIPE_CRC_RES_1_B_IVB          0x61064
-#define _PIPE_CRC_RES_2_B_IVB          0x61068
-#define _PIPE_CRC_RES_3_B_IVB          0x6106c
-#define _PIPE_CRC_RES_4_B_IVB          0x61070
-#define _PIPE_CRC_RES_5_B_IVB          0x61074
-
-#define PIPE_CRC_CTL(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
 #define PIPE_CRC_RES_1_IVB(pipe)               _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
+
+#define _PIPE_CRC_RES_2_A_IVB          0x60068
+#define _PIPE_CRC_RES_2_B_IVB          0x61068
 #define PIPE_CRC_RES_2_IVB(pipe)               _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
+
+#define _PIPE_CRC_RES_3_A_IVB          0x6006c
+#define _PIPE_CRC_RES_3_B_IVB          0x6106c
 #define PIPE_CRC_RES_3_IVB(pipe)               _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
+
+#define _PIPE_CRC_RES_4_A_IVB          0x60070
+#define _PIPE_CRC_RES_4_B_IVB          0x61070
 #define PIPE_CRC_RES_4_IVB(pipe)               _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
-#define PIPE_CRC_RES_5_IVB(pipe)               _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
 
-#define PIPE_CRC_RES_RED(dev_priv, pipe)               _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
-#define PIPE_CRC_RES_GREEN(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
-#define PIPE_CRC_RES_BLUE(dev_priv, pipe)              _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
-#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
-#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)  _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
+#define _PIPE_CRC_RES_5_A_IVB          0x60074
+#define _PIPE_CRC_RES_5_B_IVB          0x61074
+#define PIPE_CRC_RES_5_IVB(pipe)               _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
 
 #endif /* __INTEL_PIPE_CRC_REGS_H__ */