drm/i915/psr: Rename has_psr2 as has_sel_update

We are going to reuse has_psr2 for panel_replay as well. Rename it
as has_sel_update to avoid confusion.

v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp
v2: Rebase

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-2-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index ccaa4cb2809b077da8a5338ff4c604d103299255..1da4c122c52ecee9c2b0bf795a28f0d9db45acaf 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -251,9 +251,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
                drm_printf(&p, "sdp split: %s\n",
                           str_enabled_disabled(pipe_config->sdp_split_enable));
 
-               drm_printf(&p, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",
+               drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n",
                           str_enabled_disabled(pipe_config->has_psr),
-                          str_enabled_disabled(pipe_config->has_psr2),
+                          str_enabled_disabled(pipe_config->has_sel_update),
                           str_enabled_disabled(pipe_config->has_panel_replay),
                           str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
        }

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ef986b50843179b2521a6bc53061dbb0c4c0fc64..4035b3ec311d4c93226716088cf889a250cbfd34 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5320,7 +5320,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
         */
        if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
                PIPE_CONF_CHECK_BOOL(has_psr);
-               PIPE_CONF_CHECK_BOOL(has_psr2);
+               PIPE_CONF_CHECK_BOOL(has_sel_update);
                PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
                PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
                PIPE_CONF_CHECK_BOOL(has_panel_replay);

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fec3de25ea54e32327e971daaac809cecfcc6a69..10e41e67b569dd058635969c031952bce6566320 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1194,7 +1194,7 @@ struct intel_crtc_state {
 
        /* PSR is supported but might not be enabled due the lack of enabled planes */
        bool has_psr;
-       bool has_psr2;
+       bool has_sel_update;
        bool enable_psr2_sel_fetch;
        bool enable_psr2_su_region_et;
        bool req_psr2_sdp_prior_scanline;

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6b8a94d0ca9992a27d05faccb55ee7d819844f52..a6ddeadb61db39b2e67757bce114b92423d41bbd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2663,7 +2663,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
        if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
                intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
                                                 vsc);
-       } else if (crtc_state->has_psr2) {
+       } else if (crtc_state->has_sel_update) {
                /*
                 * [PSR2 without colorimetry]
                 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 151dcd0c45b60cbdfefd7b0e4f2e65f66b1cfd83..984f13d8c0c8884d616dbfd9a5d17a3c8440d7eb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
         * Recommendation is to keep this combination disabled
         * Bspec: 50422 HSD: 14010260002
         */
-       if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
+       if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
                plane_state->no_fbc_reason = "PSR2 enabled";
                return 0;
        }

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 595eb1b3b6c6afdf21dd54ae7c5ec8afeff11dc1..74e2ee9a48fa458c58f80c310fdce0fac36e6532 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -653,7 +653,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        u8 dpcd_val = DP_PSR_ENABLE;
 
-       if (crtc_state->has_psr2) {
+       if (crtc_state->has_sel_update) {
                /* Enable ALPM at sink for psr2 */
                if (!crtc_state->has_panel_replay) {
                        drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -1644,7 +1644,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
        if (!crtc_state->has_psr)
                return;
 
-       crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
+       crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
@@ -1677,7 +1677,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
                pipe_config->has_psr = true;
        }
 
-       pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
+       pipe_config->has_sel_update = intel_dp->psr.psr2_enabled;
        pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 
        if (!intel_dp->psr.psr2_enabled)
@@ -1971,7 +1971,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 
        drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
 
-       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+       intel_dp->psr.psr2_enabled = crtc_state->has_sel_update;
        intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
        intel_dp->psr.busy_frontbuffer_bits = 0;
        intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
@@ -2702,7 +2702,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
                needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
                needs_to_disable |= !new_crtc_state->has_psr;
                needs_to_disable |= !new_crtc_state->active_planes;
-               needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
+               needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled;
                needs_to_disable |= DISPLAY_VER(i915) < 11 &&
                        new_crtc_state->wm_level_disabled;