}
 EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
 
+int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
+{
+       return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_TAPDELAY_BYPASS,
+                                  index, value, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_set_tapdelay_bypass);
+
 /**
  * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
  * @value:     Status value to be written
 
 };
 
 enum pm_ioctl_id {
+       IOCTL_SET_TAPDELAY_BYPASS = 4,
        IOCTL_SD_DLL_RESET = 6,
        IOCTL_SET_SD_TAPDELAY = 7,
        IOCTL_SET_PLL_FRAC_MODE = 8,
        ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 };
 
+enum tap_delay_signal_type {
+       PM_TAPDELAY_NAND_DQS_IN = 0,
+       PM_TAPDELAY_NAND_DQS_OUT = 1,
+       PM_TAPDELAY_QSPI = 2,
+       PM_TAPDELAY_MAX = 3,
+};
+
+enum tap_delay_bypass_ctrl {
+       PM_TAPDELAY_BYPASS_DISABLE = 0,
+       PM_TAPDELAY_BYPASS_ENABLE = 1,
+};
+
 enum ospi_mux_select_type {
        PM_OSPI_MUX_SEL_DMA = 0,
        PM_OSPI_MUX_SEL_LINEAR = 1,
 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 int zynqmp_pm_write_pggs(u32 index, u32 value);
 int zynqmp_pm_read_pggs(u32 index, u32 *value);
+int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 int zynqmp_pm_set_boot_health_status(u32 value);
 int zynqmp_pm_pinctrl_request(const u32 pin);
        return -ENODEV;
 }
 
+static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
+{
+       return -ENODEV;
+}
+
 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 {
        return -ENODEV;