drm/amdgpu: Added ASIC specific check in gmc v9.0 ECC interrupt programming sequence

Devices newer then VEGA10/12 shall have these programming sequences performed by PSP BL

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index fa025ceeea0fa1e68ee9e7e6e71631e7f61e0250..68f9a1fa6dc1f3b70075db4ec377ee11439d90d2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -207,6 +207,11 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 {
        u32 bits, i, tmp, reg;
 
+       /* Devices newer then VEGA10/12 shall have these programming
+            sequences performed by PSP BL */
+       if (adev->asic_type >= CHIP_VEGA20)
+               return 0;
+
        bits = 0x7f;
 
        switch (state) {