&pipe_config->hw.adjusted_mode;
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        struct link_config_limits limits;
+       bool joiner_needs_dsc = false;
        int ret;
 
        limits.min_rate = intel_dp_common_rate(intel_dp, 0);
                                    adjusted_mode->crtc_clock))
                pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
 
+       /*
+        * Pipe joiner needs compression up to display 12 due to bandwidth
+        * limitation. DG2 onwards pipe joiner can be enabled without
+        * compression.
+        */
+       joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
+
        /*
         * Optimize for slow and wide for everything, because there are some
         * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
         */
        ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
 
-       /*
-        * Pipe joiner needs compression upto display12 due to BW limitation. DG2
-        * onwards pipe joiner can be enabled without compression.
-        */
-       drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
-       if (ret || intel_dp->force_dsc_en ||
-           (DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes)) {
+       if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
+               drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
+                           str_yes_no(ret), str_yes_no(joiner_needs_dsc),
+                           str_yes_no(intel_dp->force_dsc_en));
                ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
                                                  conn_state, &limits);
                if (ret < 0)