#define LPSS_TX_HITHRESH_DFLT  224
 
 /* Offset from drv_data->lpss_base */
+#define GENERAL_REG            0x08
+#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
 #define SSP_REG                        0x0c
 #define SPI_CS_CONTROL         0x18
 #define SPI_CS_CONTROL_SW_MODE BIT(0)
        __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
 
        /* Enable multiblock DMA transfers */
-       if (drv_data->master_info->enable_dma)
+       if (drv_data->master_info->enable_dma) {
                __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
+
+               value = __lpss_ssp_read_priv(drv_data, GENERAL_REG);
+               value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
+               __lpss_ssp_write_priv(drv_data, GENERAL_REG, value);
+       }
 }
 
 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)