#define CSI2RX_STREAM_STATUS_RDY                       BIT(31)
 
 #define CSI2RX_STREAM_DATA_CFG_REG(n)          (CSI2RX_STREAM_BASE(n) + 0x008)
-#define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT            BIT(31)
 #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n)            BIT((n) + 16)
 
 #define CSI2RX_STREAM_CFG_REG(n)               (CSI2RX_STREAM_BASE(n) + 0x00c)
                writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
                       csi2rx->base + CSI2RX_STREAM_CFG_REG(i));
 
-               writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT |
-                      CSI2RX_STREAM_DATA_CFG_VC_SELECT(i),
+               /*
+                * Enable one virtual channel. When multiple virtual channels
+                * are supported this will have to be changed.
+                */
+               writel(CSI2RX_STREAM_DATA_CFG_VC_SELECT(0),
                       csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i));
 
                writel(CSI2RX_STREAM_CTRL_START,