x86/cpufeature: Blacklist SPEC_CTRL/PRED_CMD on early Spectre v2 microcodes

This doesn't refuse to load the affected microcodes; it just refuses to
use the Spectre v2 mitigation features if they're detected, by clearing
the appropriate feature bits.

The AMD CPUID bits are handled here too, because hypervisors *may* have
been exposing those bits even on Intel chips, for fine-grained control
of what's available.

It is non-trivial to use x86_match_cpu() for this table because that
doesn't handle steppings. And the approach taken in commit bd9240a18
almost made me lose my lunch.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: gnomes@lxorguk.ukuu.org.uk
Cc: ak@linux.intel.com
Cc: ashok.raj@intel.com
Cc: dave.hansen@intel.com
Cc: karahmed@amazon.de
Cc: arjan@linux.intel.com
Cc: torvalds@linux-foundation.org
Cc: peterz@infradead.org
Cc: bp@alien8.de
Cc: pbonzini@redhat.com
Cc: tim.c.chen@linux.intel.com
Cc: gregkh@linux-foundation.org
Link: https://lkml.kernel.org/r/1516896855-7642-7-git-send-email-dwmw@amazon.co.uk
(cherry picked from commit a5b2966364538a0e68c9fa29bc0a3a1651799035)

Orabug: 27477743
CVE: CVE-2017-5715

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 Conflicts:
	arch/x86/kernel/cpu/intel.c

[Our resolution to
 5d10cbc91d9e x86/cpufeatures: Add AMD feature bits for Speculation Control
 is different, so we still clear the right bits if there (or would be)are AMD machines
 with bad microcode]

Reviewed-by: Pavel Tatashin <pasha.tatashin@oracle.com>

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 50163fa9034f0d2f4db28767432a249ad9e0cb35..e559d309672c369380fb6939764d3c82ec971d89 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -25,6 +25,60 @@
 #include <asm/apic.h>
 #endif
 
+#include <asm/intel-family.h>
+/*
+ * Early microcode releases for the Spectre v2 mitigation were broken.
+ * Information taken from;
+ * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/microcode-update-guidance.pdf
+ * - https://kb.vmware.com/s/article/52345
+ * - Microcode revisions observed in the wild
+ * - Release note from 20180108 microcode release
+ */
+struct sku_microcode {
+       u8 model;
+       u8 stepping;
+       u32 microcode;
+};
+static const struct sku_microcode spectre_bad_microcodes[] = {
+       { INTEL_FAM6_KABYLAKE_DESKTOP,  0x0B,   0x84 },
+       { INTEL_FAM6_KABYLAKE_DESKTOP,  0x0A,   0x84 },
+       { INTEL_FAM6_KABYLAKE_DESKTOP,  0x09,   0x84 },
+       { INTEL_FAM6_KABYLAKE_MOBILE,   0x0A,   0x84 },
+       { INTEL_FAM6_KABYLAKE_MOBILE,   0x09,   0x84 },
+       { INTEL_FAM6_SKYLAKE_X,         0x03,   0x0100013e },
+       { INTEL_FAM6_SKYLAKE_X,         0x04,   0x0200003c },
+       { INTEL_FAM6_SKYLAKE_MOBILE,    0x03,   0xc2 },
+       { INTEL_FAM6_SKYLAKE_DESKTOP,   0x03,   0xc2 },
+       { INTEL_FAM6_BROADWELL_CORE,    0x04,   0x28 },
+       { INTEL_FAM6_BROADWELL_GT3E,    0x01,   0x1b },
+       { INTEL_FAM6_BROADWELL_XEON_D,  0x02,   0x14 },
+       { INTEL_FAM6_BROADWELL_XEON_D,  0x03,   0x07000011 },
+       { INTEL_FAM6_BROADWELL_X,       0x01,   0x0b000025 },
+       { INTEL_FAM6_HASWELL_ULT,       0x01,   0x21 },
+       { INTEL_FAM6_HASWELL_GT3E,      0x01,   0x18 },
+       { INTEL_FAM6_HASWELL_CORE,      0x03,   0x23 },
+       { INTEL_FAM6_HASWELL_X,         0x02,   0x3b },
+       { INTEL_FAM6_HASWELL_X,         0x04,   0x10 },
+       { INTEL_FAM6_IVYBRIDGE_X,       0x04,   0x42a },
+       /* Updated in the 20180108 release; blacklist until we know otherwise */
+       { INTEL_FAM6_ATOM_GEMINI_LAKE,  0x01,   0x22 },
+       /* Observed in the wild */
+       { INTEL_FAM6_SANDYBRIDGE_X,     0x06,   0x61b },
+       { INTEL_FAM6_SANDYBRIDGE_X,     0x07,   0x712 },
+};
+
+static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
+               if (c->x86_model == spectre_bad_microcodes[i].model &&
+                   c->x86_mask == spectre_bad_microcodes[i].stepping)
+                       return (c->microcode <= spectre_bad_microcodes[i].microcode);
+       }
+       return false;
+}
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
        u64 misc_enable;
@@ -51,6 +105,13 @@ static void early_init_intel(struct cpuinfo_x86 *c)
                rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
        }
 
+       if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
+            cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
+               pr_warn("Intel Spectre v2 broken microcode detected; disabling SPEC_CTRL\n");
+               clear_cpu_cap(c, X86_FEATURE_SPEC_CTRL);
+               clear_cpu_cap(c, X86_FEATURE_IBPB);
+               clear_cpu_cap(c, X86_FEATURE_STIBP);
+       }
        /*
         * Atom erratum AAE44/AAF40/AAG38/AAH41:
         *