return 0;
        }
 
+       /* Reset the underrun counter */
+       pipe->underrun_count = 0;
+
        drm_pipe->width = cfg->width;
        drm_pipe->height = cfg->height;
        pipe->interlaced = cfg->interlaced;
 
 
 static irqreturn_t vsp1_irq_handler(int irq, void *data)
 {
-       u32 mask = VI6_WPF_IRQ_STA_DFE | VI6_WPF_IRQ_STA_FRE;
+       u32 mask = VI6_WPF_IRQ_STA_DFE | VI6_WPF_IRQ_STA_FRE |
+                  VI6_WPF_IRQ_STA_UND;
        struct vsp1_device *vsp1 = data;
        irqreturn_t ret = IRQ_NONE;
        unsigned int i;
                status = vsp1_read(vsp1, VI6_WPF_IRQ_STA(i));
                vsp1_write(vsp1, VI6_WPF_IRQ_STA(i), ~status & mask);
 
+               if ((status & VI6_WPF_IRQ_STA_UND) && wpf->entity.pipe) {
+                       wpf->entity.pipe->underrun_count++;
+
+                       dev_warn_ratelimited(vsp1->dev,
+                               "Underrun occurred at WPF%u (total underruns %u)\n",
+                               i, wpf->entity.pipe->underrun_count);
+               }
+
                if (status & VI6_WPF_IRQ_STA_DFE) {
                        vsp1_pipeline_frame_end(wpf->entity.pipe);
                        ret = IRQ_HANDLED;
 
 #define VI6_STATUS_SYS_ACT(n)          BIT((n) + 8)
 
 #define VI6_WPF_IRQ_ENB(n)             (0x0048 + (n) * 12)
+#define VI6_WPF_IRQ_ENB_UNDE           BIT(16)
 #define VI6_WPF_IRQ_ENB_DFEE           BIT(1)
 #define VI6_WPF_IRQ_ENB_FREE           BIT(0)
 
 #define VI6_WPF_IRQ_STA(n)             (0x004c + (n) * 12)
+#define VI6_WPF_IRQ_STA_UND            BIT(16)
 #define VI6_WPF_IRQ_STA_DFE            BIT(1)
 #define VI6_WPF_IRQ_STA_FRE            BIT(0)