if (port->gop_id == 0) {
                /* Enable the XLG/GIG irqs for this port */
                val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
-               if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
+               if (mvpp2_is_xlg(port->phy_interface))
                        val |= MVPP22_XLG_EXT_INT_MASK_XLG;
                else
                        val |= MVPP22_XLG_EXT_INT_MASK_GIG;
 
        mvpp22_gop_mask_irq(port);
 
-       if (port->gop_id == 0 &&
-           port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
+       if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
                val = readl(port->base + MVPP22_XLG_INT_STAT);
                if (val & MVPP22_XLG_INT_STAT_LINK) {
                        event = true;
        bool change_interface = port->phy_interface != state->interface;
 
        /* Check for invalid configuration */
-       if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) {
+       if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) {
                netdev_err(dev, "Invalid mode on %s\n", dev->name);
                return;
        }
        }
 
        /* mac (re)configuration */
-       if (state->interface == PHY_INTERFACE_MODE_10GKR)
+       if (mvpp2_is_xlg(state->interface))
                mvpp2_xlg_config(port, mode, state);
        else if (phy_interface_mode_is_rgmii(state->interface) ||
                 phy_interface_mode_is_8023z(state->interface) ||
        struct mvpp2_port *port = netdev_priv(dev);
        u32 val;
 
-       if (!phylink_autoneg_inband(mode) &&
-           interface != PHY_INTERFACE_MODE_10GKR) {
+       if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) {
                val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
                val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
                val |= MVPP2_GMAC_FORCE_LINK_PASS;
        struct mvpp2_port *port = netdev_priv(dev);
        u32 val;
 
-       if (!phylink_autoneg_inband(mode) &&
-           interface != PHY_INTERFACE_MODE_10GKR) {
+       if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) {
                val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
                val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
                val |= MVPP2_GMAC_FORCE_LINK_DOWN;