- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
 
 Optional properties:
-- clocks: Reference to the crypto engine clock.
+- clocks: Reference to the crypto engine clocks, the second clock is
+          needed for the Armada 7K/8K SoCs.
+- clock-names: mandatory if there is a second clock, in this case the
+               name must be "core" for the first clock and "reg" for
+               the second one.
 
 Example:
 
 
                }
        }
 
+       priv->reg_clk = devm_clk_get(&pdev->dev, "reg");
+       ret = PTR_ERR_OR_ZERO(priv->reg_clk);
+       /* The clock isn't mandatory */
+       if  (ret != -ENOENT) {
+               if (ret)
+                       goto err_core_clk;
+
+               ret = clk_prepare_enable(priv->reg_clk);
+               if (ret) {
+                       dev_err(dev, "unable to enable reg clk (%d)\n", ret);
+                       goto err_core_clk;
+               }
+       }
+
        ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
        if (ret)
-               goto err_clk;
+               goto err_reg_clk;
 
        priv->context_pool = dmam_pool_create("safexcel-context", dev,
                                              sizeof(struct safexcel_context_record),
                                              1, 0);
        if (!priv->context_pool) {
                ret = -ENOMEM;
-               goto err_clk;
+               goto err_reg_clk;
        }
 
        safexcel_configure(priv);
                                                     &priv->ring[i].cdr,
                                                     &priv->ring[i].rdr);
                if (ret)
-                       goto err_clk;
+                       goto err_reg_clk;
 
                ring_irq = devm_kzalloc(dev, sizeof(*ring_irq), GFP_KERNEL);
                if (!ring_irq) {
                        ret = -ENOMEM;
-                       goto err_clk;
+                       goto err_reg_clk;
                }
 
                ring_irq->priv = priv;
                                                ring_irq);
                if (irq < 0) {
                        ret = irq;
-                       goto err_clk;
+                       goto err_reg_clk;
                }
 
                priv->ring[i].work_data.priv = priv;
                priv->ring[i].workqueue = create_singlethread_workqueue(wq_name);
                if (!priv->ring[i].workqueue) {
                        ret = -ENOMEM;
-                       goto err_clk;
+                       goto err_reg_clk;
                }
 
                priv->ring[i].requests = 0;
        ret = safexcel_hw_init(priv);
        if (ret) {
                dev_err(dev, "EIP h/w init failed (%d)\n", ret);
-               goto err_clk;
+               goto err_reg_clk;
        }
 
        ret = safexcel_register_algorithms(priv);
        if (ret) {
                dev_err(dev, "Failed to register algorithms (%d)\n", ret);
-               goto err_clk;
+               goto err_reg_clk;
        }
 
        return 0;
 
-err_clk:
+err_reg_clk:
+       clk_disable_unprepare(priv->reg_clk);
+err_core_clk:
        clk_disable_unprepare(priv->clk);
        return ret;
 }