drm/amd/display: Update V_UPDATE whenever VSTARTUP changes

[Why]
If VSTARTUP changes due to bandwidth requirements, we must
recalculate and update VLINE2 as well for proper flip reporting.

[How]
After all calls to program_global_sync which reconfigures
VSTARTUP, also make sure to update V_UPDATE (i.e. VLINE2 on DCNx).

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 2fe29526532cdba76a46cf31b86cf06aec9647de..32bf6cf09677da605d02e26783b25d4adb80822b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2511,8 +2511,10 @@ static void program_all_pipe_in_tree(
                pipe_ctx->stream_res.tg->funcs->set_vtg_params(
                                pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 
-               dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+               if (dc->hwss.setup_vupdate_interrupt)
+                       dc->hwss.setup_vupdate_interrupt(pipe_ctx);
 
+               dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
        }
 
        if (pipe_ctx->plane_state != NULL)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 84aae9c05781e063e8c90aa0d7516426c02292ae..1b4aac185f3fc6da9efb200ab0b8085485d123a7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1370,6 +1370,9 @@ static void dcn20_program_pipe(
 
                pipe_ctx->stream_res.tg->funcs->set_vtg_params(
                                pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+               if (dc->hwss.setup_vupdate_interrupt)
+                       dc->hwss.setup_vupdate_interrupt(pipe_ctx);
        }
 
        if (pipe_ctx->update_flags.bits.odm)
@@ -1581,8 +1584,12 @@ bool dcn20_update_bandwidth(
 
                        pipe_ctx->stream_res.tg->funcs->set_vtg_params(
                                        pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
                        if (pipe_ctx->prev_odm_pipe == NULL)
                                dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+
+                       if (dc->hwss.setup_vupdate_interrupt)
+                               dc->hwss.setup_vupdate_interrupt(pipe_ctx);
                }
 
                pipe_ctx->plane_res.hubp->funcs->hubp_setup(