{
        struct ath5k_hw *ah;
        struct pci_dev *pdev = sc->pdev;
+       struct ath5k_eeprom_info *ee;
        int ret;
        u32 srev;
 
                goto err_free;
        }
 
+       /* Crypto settings */
+       ee = &ah->ah_capabilities.cap_eeprom;
+       ah->ah_aes_support =
+               (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
+                !AR5K_EEPROM_AES_DIS(ee->ee_misc5) &&
+                (ah->ah_mac_version > (AR5K_SREV_AR5212 >> 4) ||
+                 (ah->ah_mac_version == (AR5K_SREV_AR5212 >> 4) &&
+                  ah->ah_mac_revision >= (AR5K_SREV_AR5211 >> 4))));
+
        if (srev >= AR5K_SREV_AR2414) {
                ah->ah_combined_mic = true;
                AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,