drm/i915: Move number of scalers initialization to runtime init

In future patches, we require greater flexibility in describing
the number of scalers available on each CRTC. To ease that transition
we move the current assignment to intel_device_info.

Scaler structure initialisation is done if scaler is available on the CRTC.
Gen9 check is not required as on depending upon numbers of scalers we
initialize scalers or return without doing anything in skl_init_scalers.

v3: Changed skl_init_scaler to intel_crtc_init_scalers

v2: Added Chris's comments.

Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480398794-22741-1-git-send-email-nabendu.bikash.maiti@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ab499c76e8bdb6a9084e6462de38abe2faeeb1d5..c2e7011026b114f69983d850d85b4a444f908afc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -873,6 +873,7 @@ struct intel_device_info {
        u16 device_id;
        u8 num_pipes;
        u8 num_sprites[I915_MAX_PIPES];
+       u8 num_scalers[I915_MAX_PIPES];
        u8 gen;
        u16 gen_mask;
        enum intel_platform platform;

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index c46415b8c1b93bb4309719f2e56fef4b8b927ee3..1b5ffc4b63b248a396e3aac944da1601e6dc2af5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -325,6 +325,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                info->num_sprites[PIPE_A] = 2;
                info->num_sprites[PIPE_B] = 2;
                info->num_sprites[PIPE_C] = 1;
+               info->num_scalers[PIPE_A] = 2;
+               info->num_scalers[PIPE_B] = 2;
+               info->num_scalers[PIPE_C] = 1;
        } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
                for_each_pipe(dev_priv, pipe)
                        info->num_sprites[pipe] = 2;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fba9734d14aa32abbe90831071abed4413e2a3a4..287b35a39e18ecf3f1eec86c92ad6bbc82ec8125 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -115,9 +115,8 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
                            const struct intel_crtc_state *pipe_config);
 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
-static void skl_init_scalers(struct drm_i915_private *dev_priv,
-                            struct intel_crtc *crtc,
-                            struct intel_crtc_state *crtc_state);
+static void intel_crtc_init_scalers(struct intel_crtc *crtc,
+                                   struct intel_crtc_state *crtc_state);
 static void skylake_pfit_enable(struct intel_crtc *crtc);
 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 static void ironlake_pfit_enable(struct intel_crtc *crtc);
@@ -10745,7 +10744,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
                I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
 
        if (INTEL_GEN(dev_priv) >= 9) {
-               skl_init_scalers(dev_priv, crtc, pipe_config);
+               intel_crtc_init_scalers(crtc, pipe_config);
 
                pipe_config->scaler_state.scaler_id = -1;
                pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
@@ -15273,14 +15272,18 @@ fail:
        return ERR_PTR(ret);
 }
 
-static void skl_init_scalers(struct drm_i915_private *dev_priv,
-                            struct intel_crtc *crtc,
-                            struct intel_crtc_state *crtc_state)
+static void intel_crtc_init_scalers(struct intel_crtc *crtc,
+                                   struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc_scaler_state *scaler_state =
                &crtc_state->scaler_state;
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        int i;
 
+       crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
+       if (!crtc->num_scalers)
+               return;
+
        for (i = 0; i < crtc->num_scalers; i++) {
                struct intel_scaler *scaler = &scaler_state->scalers[i];
 
@@ -15312,16 +15315,6 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
        intel_crtc->base.state = &crtc_state->base;
        crtc_state->base.crtc = &intel_crtc->base;
 
-       /* initialize shared scalers */
-       if (INTEL_GEN(dev_priv) >= 9) {
-               if (pipe == PIPE_C)
-                       intel_crtc->num_scalers = 1;
-               else
-                       intel_crtc->num_scalers = SKL_NUM_SCALERS;
-
-               skl_init_scalers(dev_priv, intel_crtc, crtc_state);
-       }
-
        primary = intel_primary_plane_create(dev_priv, pipe);
        if (IS_ERR(primary)) {
                ret = PTR_ERR(primary);
@@ -15363,6 +15356,9 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 
        intel_crtc->wm.cxsr_allowed = true;
 
+       /* initialize shared scalers */
+       intel_crtc_init_scalers(intel_crtc, crtc_state);
+
        BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
               dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
        dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;