the ixcurrent_pg_status addr is different between APU and DGPU.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 
        mutex_lock(&adev->pm.mutex);
 
-       if (RREG32_SMC(ixCURRENT_PG_STATUS) &
-                               CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
+       if (adev->flags & AMD_IS_APU)
+               data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
+       else
+               data = RREG32_SMC(ixCURRENT_PG_STATUS);
+
+       if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
                DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
                goto out;
        }
 
 
        mutex_lock(&adev->pm.mutex);
 
-       if (RREG32_SMC(ixCURRENT_PG_STATUS) &
-                       CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) {
+       if (adev->flags & AMD_IS_APU)
+               data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
+       else
+               data = RREG32_SMC(ixCURRENT_PG_STATUS);
+
+       if (data & CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) {
                DRM_INFO("Cannot get clockgating state when VCE is powergated.\n");
                goto out;
        }
 
 #define ixROM_SW_DATA_63                                                        0xc0600120
 #define ixROM_SW_DATA_64                                                        0xc0600124
 #define ixCURRENT_PG_STATUS                                                     0xc020029c
+#define ixCURRENT_PG_STATUS_APU                                                 0xd020029c
 
 #endif /* SMU_7_1_2_D_H */
 
 #define ixGC_CAC_ACC_CU15                                                       0xc9
 #define ixGC_CAC_OVRD_CU                                                        0xe7
 #define ixCURRENT_PG_STATUS                                                     0xc020029c
+#define ixCURRENT_PG_STATUS_APU                                                 0xd020029c
+
 #endif /* SMU_7_1_3_D_H */