intel_ddi_enable_pipe_clock(intel_crtc);
 
-       if (INTEL_INFO(dev)->gen == 9)
+       if (INTEL_INFO(dev)->gen >= 9)
                skylake_pfit_enable(intel_crtc);
-       else if (INTEL_INFO(dev)->gen < 9)
-               ironlake_pfit_enable(intel_crtc);
        else
-               MISSING_CASE(INTEL_INFO(dev)->gen);
+               ironlake_pfit_enable(intel_crtc);
 
        /*
         * On ILK+ LUT must be loaded before the pipe is running but with
 
        intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
-       if (INTEL_INFO(dev)->gen == 9)
+       if (INTEL_INFO(dev)->gen >= 9)
                skylake_scaler_disable(intel_crtc);
-       else if (INTEL_INFO(dev)->gen < 9)
-               ironlake_pfit_disable(intel_crtc);
        else
-               MISSING_CASE(INTEL_INFO(dev)->gen);
+               ironlake_pfit_disable(intel_crtc);
 
        intel_ddi_disable_pipe_clock(intel_crtc);
 
        }
 
        if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
-               if (INTEL_INFO(dev)->gen == 9)
+               if (INTEL_INFO(dev)->gen >= 9)
                        skylake_get_pfit_config(crtc, pipe_config);
-               else if (INTEL_INFO(dev)->gen < 9)
-                       ironlake_get_pfit_config(crtc, pipe_config);
                else
-                       MISSING_CASE(INTEL_INFO(dev)->gen);
+                       ironlake_get_pfit_config(crtc, pipe_config);
        }
 
        if (IS_HASWELL(dev))