{
        enum bp_result result = BP_RESULT_OK;
        struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
+       struct atom_smu_info_v3_3 *smu_info = NULL;
 
        if (!ss_info)
                return BP_RESULT_BADINPUT;
        if (!disp_cntl_tbl)
                return BP_RESULT_BADBIOSTABLE;
 
+
        ss_info->type.STEP_AND_DELAY_INFO = false;
        ss_info->spread_percentage_divider = 1000;
        /* BIOS no longer uses target clock.  Always enable for now */
                 */
                result = BP_RESULT_UNSUPPORTED;
                break;
+       case AS_SIGNAL_TYPE_XGMI:
+               smu_info =  GET_IMAGE(struct atom_smu_info_v3_3,
+                                     DATA_TABLES(smu_info));
+               if (!smu_info)
+                       return BP_RESULT_BADBIOSTABLE;
+
+               ss_info->spread_spectrum_percentage =
+                               smu_info->waflclk_ss_percentage;
+               ss_info->spread_spectrum_range =
+                               smu_info->gpuclk_ss_rate_10hz * 10;
+               if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+                       ss_info->type.CENTER_MODE = true;
+               break;
        default:
                result = BP_RESULT_UNSUPPORTED;
        }