release_region(ioport, ITE_887x_IOSIZE);
 }
 
+/*
+ * EndRun Technologies.
+ * Determine the number of ports available on the device.
+ */
+#define PCI_VENDOR_ID_ENDRUN                   0x7401
+#define PCI_DEVICE_ID_ENDRUN_1588      0xe100
+
+static int pci_endrun_init(struct pci_dev *dev)
+{
+       u8 __iomem *p;
+       unsigned long deviceID;
+       unsigned int  number_uarts = 0;
+
+       /* EndRun device is all 0xexxx */
+       if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
+               (dev->device & 0xf000) != 0xe000)
+               return 0;
+
+       p = pci_iomap(dev, 0, 5);
+       if (p == NULL)
+               return -ENOMEM;
+
+       deviceID = ioread32(p);
+       /* EndRun device */
+       if (deviceID == 0x07000200) {
+               number_uarts = ioread8(p + 4);
+               dev_dbg(&dev->dev,
+                       "%d ports detected on EndRun PCI Express device\n",
+                       number_uarts);
+       }
+       pci_iounmap(dev, p);
+       return number_uarts;
+}
+
 /*
  * Oxford Semiconductor Inc.
  * Check that device is part of the Tornado range of devices, then determine
                .init           = pci_netmos_init,
                .setup          = pci_netmos_9900_setup,
        },
+       /*
+        * EndRun Technologies
+       */
+       {
+               .vendor         = PCI_VENDOR_ID_ENDRUN,
+               .device         = PCI_ANY_ID,
+               .subvendor      = PCI_ANY_ID,
+               .subdevice      = PCI_ANY_ID,
+               .init           = pci_endrun_init,
+               .setup          = pci_default_setup,
+       },
        /*
         * For Oxford Semiconductor Tornado based devices
         */
        pbn_panacom2,
        pbn_panacom4,
        pbn_plx_romulus,
+       pbn_endrun_2_4000000,
        pbn_oxsemi,
        pbn_oxsemi_1_4000000,
        pbn_oxsemi_2_4000000,
                .first_offset   = 0x03,
        },
 
+       /*
+        * EndRun Technologies
+       * Uses the size of PCI Base region 0 to
+       * signal now many ports are available
+       * 2 port 952 Uart support
+       */
+       [pbn_endrun_2_4000000] = {
+               .flags          = FL_BASE0,
+               .num_ports      = 2,
+               .base_baud      = 4000000,
+               .uart_offset    = 0x200,
+               .first_offset   = 0x1000,
+       },
+
        /*
         * This board uses the size of PCI Base region 0 to
         * signal now many ports are available
        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
                0x10b5, 0x106a, 0, 0,
                pbn_plx_romulus },
+       /*
+       * EndRun Technologies. PCI express device range.
+       *    EndRun PTP/1588 has 2 Native UARTs.
+       */
+       {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
+               PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+               pbn_endrun_2_4000000 },
        /*
         * Quatech cards. These actually have configurable clocks but for
         * now we just use the default.