bnx2x: add RSS capability for GRE traffic

The patch drives FW to perform RSS for GRE traffic,
based on inner headers.

Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
index 8f9637279f12d01c68cc95f5a41769ec980ad22b..f9098d8fc25b02309d44fc3a76201c8dc55b09b2 100644 (file)
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
@@ -973,6 +973,9 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
        else /* CHIP_IS_E1X */
                start_params->network_cos_mode = FW_WRR;
 
+       start_params->gre_tunnel_mode = IPGRE_TUNNEL;
+       start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS;
+
        return bnx2x_func_state_change(bp, &func_params);
 }
 

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
index 66ab259080867cf627dc3451f699860c709975c3..5bdc1d6dcf89a02b491d07cd63543804652d5892 100644 (file)
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
@@ -5679,17 +5679,18 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
        memset(rdata, 0, sizeof(*rdata));
 
        /* Fill the ramrod data with provided parameters */
-       rdata->function_mode    = (u8)start_params->mf_mode;
-       rdata->sd_vlan_tag      = cpu_to_le16(start_params->sd_vlan_tag);
-       rdata->path_id          = BP_PATH(bp);
-       rdata->network_cos_mode = start_params->network_cos_mode;
-
-       /*
-        *  No need for an explicit memory barrier here as long we would
-        *  need to ensure the ordering of writing to the SPQ element
-        *  and updating of the SPQ producer which involves a memory
-        *  read and we will have to put a full memory barrier there
-        *  (inside bnx2x_sp_post()).
+       rdata->function_mode    = (u8)start_params->mf_mode;
+       rdata->sd_vlan_tag      = cpu_to_le16(start_params->sd_vlan_tag);
+       rdata->path_id          = BP_PATH(bp);
+       rdata->network_cos_mode = start_params->network_cos_mode;
+       rdata->gre_tunnel_mode  = start_params->gre_tunnel_mode;
+       rdata->gre_tunnel_rss   = start_params->gre_tunnel_rss;
+
+       /* No need for an explicit memory barrier here as long we would
+        * need to ensure the ordering of writing to the SPQ element
+        * and updating of the SPQ producer which involves a memory
+        * read and we will have to put a full memory barrier there
+        * (inside bnx2x_sp_post()).
         */
 
        return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
index 064dba24610d1a13cd93f5e21d1d34aea35aa87f..35479da11f84c0703bc763ff6c7b7ba87fd95af6 100644 (file)
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
@@ -1123,6 +1123,15 @@ struct bnx2x_func_start_params {
 
        /* Function cos mode */
        u8 network_cos_mode;
+
+       /* NVGRE classification enablement */
+       u8 nvgre_clss_en;
+
+       /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
+       u8 gre_tunnel_mode;
+
+       /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
+       u8 gre_tunnel_rss;
 };
 
 struct bnx2x_func_switch_update_params {