clk: loongson2: Allow zero divisors for dividers

LS2K0300 and LS2K0500 ship divider clocks which allows zero divisors,
in which case the divider acts the same as one is specified.

Let's pass CLK_DIVIDER_ALLOW_ZERO when registering divider clocks to
prepare for future introduction of these clocks.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index bba97270376ce053158073f90fd7c6dabd9f78db..7a916c7d2718a0c69d644b61c742eeecfc64a9cf 100644 (file)
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -361,7 +361,8 @@ static int loongson2_clk_probe(struct platform_device *pdev)
                                                          p->parent_name, 0,
                                                          clp->base + p->reg_offset,
                                                          p->div_shift, p->div_width,
-                                                         CLK_DIVIDER_ONE_BASED,
+                                                         CLK_DIVIDER_ONE_BASED |
+                                                         CLK_DIVIDER_ALLOW_ZERO,
                                                          &clp->clk_lock);
                        break;
                case CLK_TYPE_GATE: