drm/amd/display: Add enum for H-timing divider mode

Add h_timing_div_mode enum to better reflect possible register
values. Replace previously programmed values with enum

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index b631786a4a34882ac006daa34b565cc594198fed..e5e5be63032b846174413f1d50d614a1c657d557 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -154,7 +154,7 @@ void optc1_program_timing(
        uint32_t h_sync_polarity, v_sync_polarity;
        uint32_t start_point = 0;
        uint32_t field_num = 0;
-       uint32_t h_div_2;
+       enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
 
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
@@ -285,10 +285,11 @@ void optc1_program_timing(
         * of stereo handled in explicit call
         */
 
-       h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
-       REG_UPDATE(OTG_H_TIMING_CNTL,
-                       OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->opp_count == 2);
+       if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
+               h_div = H_TIMING_DIV_BY2;
 
+       REG_UPDATE(OTG_H_TIMING_CNTL,
+               OTG_H_TIMING_DIV_BY2, h_div);
 }
 
 void optc1_set_vtg_params(struct timing_generator *optc,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 1f83cb7c7dd47b61c1a0f530aace768d27cc35c2..f607ef24c766157978bcd811b9df03e80a47702f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -96,6 +96,11 @@ enum crc_selection {
        INTERSECT_WINDOW_NOT_A_NOT_B,
 };
 
+enum h_timing_div_mode {
+       H_TIMING_NO_DIV,
+       H_TIMING_DIV_BY2,
+};
+
 struct crc_params {
        /* Regions used to calculate CRC*/
        uint16_t windowa_x_start;