pinctrl: sh-pfc: sh7264: Fix PFCR3 and PFCR0 register configuration

The Port F Control Register 3 (PFCR3) contains only a single field.
However, counting from left to right, it is the fourth field, not the
first field.
Insert the missing dummy configuration values (3 fields of 16 values) to
fix this.

The descriptor for the Port F Control Register 0 (PFCR0) lacks the
description for the 4th field (PF0 Mode, PF0MD[2:0]).
Add the missing configuration values to fix this.

Fixes: a8d42fc4217b1ea1 ("sh-pfc: Add sh7264 pinmux support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 4f44ce0d7237faa9f203ccd5f4cf2f3185b15d02..501de63e6c5f4be2bcb2bd706df746261a732cd1 100644 (file)
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -1713,6 +1713,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
        },
 
        { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
+               0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+               0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+               0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                PF12MD_000, PF12MD_001, 0, PF12MD_011,
                PF12MD_100, PF12MD_101, 0, 0,
                0, 0, 0, 0, 0, 0, 0, 0 }
@@ -1756,8 +1759,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0, 0, 0, 0, 0, 0,
                PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
                PF1MD_100, PF1MD_101, 0, 0,
-               0, 0, 0, 0, 0, 0, 0, 0
-        }
+               0, 0, 0, 0, 0, 0, 0, 0,
+               PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
+               PF0MD_100, PF0MD_101, 0, 0,
+               0, 0, 0, 0, 0, 0, 0, 0 }
        },
 
        { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {