arm64: insn: remove aarch64_insn_gen_prefetch()

There are no users of aarch64_insn_gen_prefetch(), and which encodes a
PRFM (immediate) with a hard-coded offset of 0.

Remove it for now; we can always restore it with tests if we need it in
future.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Joey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Link: https://lore.kernel.org/r/20221114135928.3000571-2-mark.rutland@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 834bff7205824040b16c43ee334687c08d98c307..03f60234e60a1ecb0db56cdf15ec9b4821c88478 100644 (file)
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -580,10 +580,6 @@ u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
                          enum aarch64_insn_register Rn,
                          enum aarch64_insn_register Rd,
                          u8 lsb);
-u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
-                             enum aarch64_insn_prfm_type type,
-                             enum aarch64_insn_prfm_target target,
-                             enum aarch64_insn_prfm_policy policy);
 #ifdef CONFIG_ARM64_LSE_ATOMICS
 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
                                  enum aarch64_insn_register address,

diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
index 49e972beeac7added30b7434a857da1dbcafcec2..ac0df03fffcdd248f6ec3fad2693a0b6ae17c618 100644 (file)
--- a/arch/arm64/lib/insn.c
+++ b/arch/arm64/lib/insn.c
@@ -816,76 +816,6 @@ u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
 }
 #endif
 
-static u32 aarch64_insn_encode_prfm_imm(enum aarch64_insn_prfm_type type,
-                                       enum aarch64_insn_prfm_target target,
-                                       enum aarch64_insn_prfm_policy policy,
-                                       u32 insn)
-{
-       u32 imm_type = 0, imm_target = 0, imm_policy = 0;
-
-       switch (type) {
-       case AARCH64_INSN_PRFM_TYPE_PLD:
-               break;
-       case AARCH64_INSN_PRFM_TYPE_PLI:
-               imm_type = BIT(0);
-               break;
-       case AARCH64_INSN_PRFM_TYPE_PST:
-               imm_type = BIT(1);
-               break;
-       default:
-               pr_err("%s: unknown prfm type encoding %d\n", __func__, type);
-               return AARCH64_BREAK_FAULT;
-       }
-
-       switch (target) {
-       case AARCH64_INSN_PRFM_TARGET_L1:
-               break;
-       case AARCH64_INSN_PRFM_TARGET_L2:
-               imm_target = BIT(0);
-               break;
-       case AARCH64_INSN_PRFM_TARGET_L3:
-               imm_target = BIT(1);
-               break;
-       default:
-               pr_err("%s: unknown prfm target encoding %d\n", __func__, target);
-               return AARCH64_BREAK_FAULT;
-       }
-
-       switch (policy) {
-       case AARCH64_INSN_PRFM_POLICY_KEEP:
-               break;
-       case AARCH64_INSN_PRFM_POLICY_STRM:
-               imm_policy = BIT(0);
-               break;
-       default:
-               pr_err("%s: unknown prfm policy encoding %d\n", __func__, policy);
-               return AARCH64_BREAK_FAULT;
-       }
-
-       /* In this case, imm5 is encoded into Rt field. */
-       insn &= ~GENMASK(4, 0);
-       insn |= imm_policy | (imm_target << 1) | (imm_type << 3);
-
-       return insn;
-}
-
-u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
-                             enum aarch64_insn_prfm_type type,
-                             enum aarch64_insn_prfm_target target,
-                             enum aarch64_insn_prfm_policy policy)
-{
-       u32 insn = aarch64_insn_get_prfm_value();
-
-       insn = aarch64_insn_encode_ldst_size(AARCH64_INSN_SIZE_64, insn);
-
-       insn = aarch64_insn_encode_prfm_imm(type, target, policy, insn);
-
-       insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
-                                           base);
-
-       return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, 0);
-}
-
 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
                                 enum aarch64_insn_register src,
                                 int imm, enum aarch64_insn_variant variant,