PCI: only save/restore existent registers in the PCIe capability

PCIe 1.1 base neither requires the endpoint to implement the entire
PCIe capability structure nor specifies default values of registers
that are not implemented by the device. So we only save and restore
registers that must be implemented by different device types if the
device PCIe capability version is 1.

PCIe 1.1 Capability Structure Expansion ECN and PCIe 2.0 requires
all registers in the PCIe capability to be either implemented or
hardwired to 0. Their PCIe capability version is 2.

Signed-off-by: Yu Zhao <yu.zhao@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 16fd0d4c316655dbcfb8729f82a9aef5cabb7e8c..34bf0fdf5047c63dc6aefebc35a8b26b8699009e 100644 (file)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -681,11 +681,34 @@ EXPORT_SYMBOL(pci_choose_state);
 
 #define PCI_EXP_SAVE_REGS      7
 
+#define pcie_cap_has_devctl(type, flags)       1
+#define pcie_cap_has_lnkctl(type, flags)               \
+               ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
+                (type == PCI_EXP_TYPE_ROOT_PORT ||     \
+                 type == PCI_EXP_TYPE_ENDPOINT ||      \
+                 type == PCI_EXP_TYPE_LEG_END))
+#define pcie_cap_has_sltctl(type, flags)               \
+               ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
+                ((type == PCI_EXP_TYPE_ROOT_PORT) ||   \
+                 (type == PCI_EXP_TYPE_DOWNSTREAM &&   \
+                  (flags & PCI_EXP_FLAGS_SLOT))))
+#define pcie_cap_has_rtctl(type, flags)                        \
+               ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
+                (type == PCI_EXP_TYPE_ROOT_PORT ||     \
+                 type == PCI_EXP_TYPE_RC_EC))
+#define pcie_cap_has_devctl2(type, flags)              \
+               ((flags & PCI_EXP_FLAGS_VERS) > 1)
+#define pcie_cap_has_lnkctl2(type, flags)              \
+               ((flags & PCI_EXP_FLAGS_VERS) > 1)
+#define pcie_cap_has_sltctl2(type, flags)              \
+               ((flags & PCI_EXP_FLAGS_VERS) > 1)
+
 static int pci_save_pcie_state(struct pci_dev *dev)
 {
        int pos, i = 0;
        struct pci_cap_saved_state *save_state;
        u16 *cap;
+       u16 flags;
 
        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
        if (pos <= 0)
@@ -698,13 +721,22 @@ static int pci_save_pcie_state(struct pci_dev *dev)
        }
        cap = (u16 *)&save_state->data[0];
 
-       pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
-       pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
-       pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
-       pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
-       pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
-       pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
-       pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
+       pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
+
+       if (pcie_cap_has_devctl(dev->pcie_type, flags))
+               pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
+       if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
+               pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
+       if (pcie_cap_has_sltctl(dev->pcie_type, flags))
+               pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
+       if (pcie_cap_has_rtctl(dev->pcie_type, flags))
+               pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
+       if (pcie_cap_has_devctl2(dev->pcie_type, flags))
+               pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
+       if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
+               pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
+       if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
+               pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
 
        return 0;
 }
@@ -714,6 +746,7 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
        int i = 0, pos;
        struct pci_cap_saved_state *save_state;
        u16 *cap;
+       u16 flags;
 
        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
@@ -721,13 +754,22 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
                return;
        cap = (u16 *)&save_state->data[0];
 
-       pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
-       pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
-       pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
-       pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
-       pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
-       pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
-       pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
+       pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
+
+       if (pcie_cap_has_devctl(dev->pcie_type, flags))
+               pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
+       if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
+               pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
+       if (pcie_cap_has_sltctl(dev->pcie_type, flags))
+               pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
+       if (pcie_cap_has_rtctl(dev->pcie_type, flags))
+               pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
+       if (pcie_cap_has_devctl2(dev->pcie_type, flags))
+               pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
+       if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
+               pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
+       if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
+               pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
 }
 
 

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index e4d08c1b2e0b40689d74911624468762eea0e281..616bf8b3c8b548707a84b6579b0d31d7f3b840ee 100644 (file)
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -376,6 +376,7 @@
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6   /* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7   /* PCI/PCI-X Bridge */
 #define  PCI_EXP_TYPE_RC_END   0x9     /* Root Complex Integrated Endpoint */
+#define  PCI_EXP_TYPE_RC_EC    0x10    /* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT     0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ      0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP         4       /* Device capabilities */