(and it uses default address).
======================================================================
-Modifications since 0.6.2:
+Modifications for 0.6.3:
======================================================================
+* Misc bug fixes
+
+* All frequencies in HZ now (internally)
+
* Add support for BOOTP Domain Name Server Option
======================================================================
char *
strmhz(char *buf, long hz)
{
- int l, n;
+ long l, n;
#if defined(CFG_CLKS_IN_HZ)
- int m;
+ long m;
#endif
n = hz / 1000000L;
- l = sprintf(buf, "%d", n);
+ l = sprintf(buf, "%ld", n);
#if defined(CFG_CLKS_IN_HZ)
m = (hz % 1000000L) / 1000L;
if (m != 0)
- sprintf(buf+l, ".%03d", m);
+ sprintf(buf+l, ".%03ld", m);
#endif
return (buf);
board_init_f (ulong bootflag)
{
bd_t *bd;
- ulong reg, len, clock_mhz;
+ ulong reg, len;
int board_type;
ulong addr_moni, addr_sp;
ulong dram_size;
#endif /* CONFIG_8260 */
-#if defined(CFG_CLKS_IN_HZ)
- clock_mhz = idata->cpu_clk; /* still in Hz */
-#else
- clock_mhz = idata->cpu_clk / 1000 / 1000; /* in MHz */
-#endif
-
s = getenv ("baudrate");
baudrate = s ? (int)simple_strtoul(s, NULL, 10) : CONFIG_BAUDRATE;
/* set up serial port */
- serial_init (clock_mhz, baudrate);
+ serial_init (idata->cpu_clk, baudrate);
/* Initialize the console (before the relocation) */
console_init_f ();
printf ("Initializing...\n CPU: "); /* Check CPU */
- if (checkcpu(clock_mhz) < 0) {
+ if (checkcpu(idata->cpu_clk) < 0) {
printf (failed);
hang();
}
s = (*e) ? e+1 : e;
}
- bd->bi_intfreq = clock_mhz; /* Internal Freq, in MHz */
- bd->bi_busfreq = get_bus_freq(clock_mhz); /* Bus Freq, in MHz */
-#if defined(CONFIG_8260)
-# if defined(CFG_CLKS_IN_HZ)
+#if defined(CFG_CLKS_IN_HZ)
+ bd->bi_intfreq = idata->cpu_clk; /* Internal Freq, in Hz */
+ bd->bi_busfreq = get_bus_freq(idata->cpu_clk); /* Bus Freq, in Hz */
+# if defined(CONFIG_8260)
bd->bi_cpmfreq = idata->cpm_clk;
bd->bi_brgfreq = idata->brg_clk;
bd->bi_sccfreq = idata->scc_clk;
- bd->bi_vco = idata->vco_out;
-# else
- bd->bi_cpmfreq = idata->cpm_clk / 1000 / 1000;
- bd->bi_brgfreq = idata->brg_clk / 1000 / 1000;
- bd->bi_sccfreq = idata->scc_clk / 1000 / 1000;
- bd->bi_vco = idata->vco_out / 1000 / 1000;
-# endif
-#endif /* CONFIG_8260 */
+ bd->bi_vco = idata->vco_out;
+# endif /* CONFIG_8260 */
+#else
+ bd->bi_intfreq = idata->cpu_clk / 1000000L;
+ bd->bi_busfreq = get_bus_freq(idata->cpu_clk) / 1000000L;
+# if defined(CONFIG_8260)
+ bd->bi_cpmfreq = idata->cpm_clk / 1000000L;
+ bd->bi_brgfreq = idata->brg_clk / 1000000L;
+ bd->bi_sccfreq = idata->scc_clk / 1000000L;
+ bd->bi_vco = idata->vco_out / 1000000L;
+# endif /* CONFIG_8260 */
+#endif /* CFG_CLKS_IN_HZ */
bd->bi_baudrate = baudrate; /* Console Baudrate */
strncpy(bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
strncpy(bd->bi_r_version, PPCBOOT_VERSION, sizeof(bd->bi_r_version));
- bd->bi_procfreq = bd->bi_intfreq * 1000000; /* Processor Speed, In Hz */
+ bd->bi_procfreq = idata->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = bd->bi_busfreq;
bd->bi_pci_busfreq = bd->bi_busfreq;
#endif
printf (" immr_base = 0x%08lx\n", bd->bi_immr_base );
#endif
printf (" bootflags = 0x%08lx\n", bd->bi_bootflags );
+#if defined(CFG_CLKS_IN_HZ)
printf (" intfreq = %6s MHz\n", strmhz(buf, bd->bi_intfreq));
printf (" busfreq = %6s MHz\n", strmhz(buf, bd->bi_busfreq));
+#else
+ printf (" intfreq = %6s MHz\n", strmhz(buf, bd->bi_intfreq*1000000L));
+ printf (" busfreq = %6s MHz\n", strmhz(buf, bd->bi_busfreq*1000000L));
+#endif /* CFG_CLKS_IN_HZ */
printf (" ethaddr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
#define CONFIG_BOOTP_ALL (~0)
#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \
- CONFIG_BOOTP_GATEWAY | \
+ CONFIG_BOOTP_GATEWAY | \
+ CONFIG_BOOTP_HOSTNAME | \
CONFIG_BOOTP_BOOTPATH)
#ifndef CONFIG_BOOTP_MASK
"nfsaddrs=10.0.0.99:10.0.0.2"
#else
#define CONFIG_BOOTARGS "root=/dev/hda1 " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0: " \
- "hda=bswap"
+ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
#endif
(CONFIG_CMD_DFL & ~(CFG_CMD_NET))
#endif /* 0 */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_COMMANDS \
((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#ifndef __CONFIG_H
#define __CONFIG_H
+#undef TQM8xxL_80MHz /* define for 80 MHz CPU only */
+
/*
* High Level Configuration Options
* (easy to change)
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
*/
+#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR \
+ ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else /* up to 50 MHz we use a 1:1 clock */
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif /* TQM8xxL_80MHz */
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
+#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR (/* SCCR_TBS | */ \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#else /* up to 50 MHz we use a 1:1 clock */
#define CFG_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
+#endif /* TQM8xxL_80MHz */
/*-----------------------------------------------------------------------
* PCMCIA stuff
#ifndef __CONFIG_H
#define __CONFIG_H
+#undef TQM8xxL_80MHz /* define for 80 MHz CPU only */
+
/*
* High Level Configuration Options
* (easy to change)
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
*/
+#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR \
+ ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else /* up to 50 MHz we use a 1:1 clock */
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif /* TQM8xxL_80MHz */
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
+#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR (/* SCCR_TBS | */ \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#else /* up to 50 MHz we use a 1:1 clock */
#define CFG_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
+#endif /* TQM8xxL_80MHz */
/*-----------------------------------------------------------------------
* PCMCIA stuff
#ifndef __CONFIG_H
#define __CONFIG_H
-#define TQM8xxL_80MHz 1 /* define for 80 MHz CPU only */
+#undef TQM8xxL_80MHz /* define for 80 MHz CPU only */
/*
* High Level Configuration Options
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#undef TQM8xxL_80MHz /* define for 80 MHz CPU only */
+
/*
* High Level Configuration Options
* (easy to change)
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
-#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
- "nfsroot=10.0.0.2:/LinuxPPC " \
- "nfsaddrs=10.0.0.99:10.0.0.2"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
*/
+#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR \
+ ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else /* up to 50 MHz we use a 1:1 clock */
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif /* TQM8xxL_80MHz */
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
+#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR (/* SCCR_TBS | */ \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#else /* up to 50 MHz we use a 1:1 clock */
#define CFG_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
+#endif /* TQM8xxL_80MHz */
/*-----------------------------------------------------------------------
* PCMCIA stuff
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "ppcboot 0.6.2"
+#define PPCBOOT_VERSION "ppcboot 0.6.3"
#endif /* __VERSION_H__ */
/* ------------------------------------------------------------------------- */
/*
- * We implement the delay by converting the delay (the number of
- * microseconds to wait) into a number of time base ticks; then we
- * watch the time base until it has incremented by that amount.
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ *
*/
-void
-udelay(unsigned long usec)
+unsigned long get_tbclk (void)
{
ulong tbclk;
- ulong ticks;
/* Pointer to initial global data area */
init_data_t *idata =
(init_data_t *)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
- tbclk = (idata->cpu_clk + 3) / 4;
- ticks = ((usec * ((tbclk + 999) / 1000)) + 999) / 1000;
+ tbclk = (idata->cpu_clk + 3L) / 4L;
- wait_ticks (ticks);
+ return (tbclk);
}
/* ------------------------------------------------------------------------- */
/****************************************************************************/
-#define DECREMENTER_TICK 1000 /* 1 ms tick */
unsigned decrementer_count; /* count val for 1e6/HZ microseconds */
struct irq_action {
interrupt_init(bd_t *bd)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
- ulong freq;
-
-#if defined(CFG_CLKS_IN_HZ)
- freq = bd->bi_intfreq / 4;
-#else
- freq = (bd->bi_intfreq * 1000000) / 4;
-#endif
- decrementer_count = freq / DECREMENTER_TICK;
+ /* Pointer to initial global data area */
+ init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
+
+ decrementer_count = (idata->cpu_clk / 4) / CFG_HZ;
/* Initialize the default interrupt mapping priorities */
immr->im_intctl.ic_sicr = 0;
* truncate - hopefully that will provide a slightly more accurate
* clock divider.
*/
-#if defined(CFG_CLKS_IN_HZ)
i = (idata->brg_clk + 15) / 16;
-#else
- i = ((idata->brg_clk * 1000000) + 15) / 16;
-#endif
i = (i + baudrate - 1) / baudrate;
* truncate - hopefully that will provide a slightly more accurate
* clock divider.
*/
-#if defined(CFG_CLKS_IN_HZ)
i = (idata->brg_clk + 15) / 16;
-#else
- i = ((idata->brg_clk * 1000000) + 15) / 16;
-#endif
i = (i + baudrate - 1) / baudrate;
init_data_t *idata = \
(init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
-#if defined(CFG_CLKS_IN_HZ)
return (idata->bus_clk);
-#else
- return (idata->bus_clk / 1000 / 1000);
-#endif
}
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
- * Get timebase clock frequency
+ * Get timebase clock frequency (like cpu_clk in Hz)
*
* See table 15-5 pp. 15-16, and SCCR[RTSEL] pp. 15-27.
*/
interrupt_init (bd_t *bd)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
- int freq;
-#if defined(CFG_CLKS_IN_HZ)
- freq = bd->bi_intfreq;
-#else
- freq = (bd->bi_intfreq * 1000000);
-#endif
- if (immr->im_clkrst.car_sccr & SCCR_TBS) {
- freq /= 16; /* use divide by 16 processor clock */
- }
- decrementer_count = freq / CFG_HZ;
+ decrementer_count = get_tbclk() / CFG_HZ;
cpm_interrupt_init();
#else
cp->cp_brgc2 = /* Console on SMC2 */
#endif
-#if defined(CFG_CLKS_IN_HZ)
- ((((cpu_clock/16) / baudrate)-1) << 1)
-#else
- (((((cpu_clock * 1000000)/16) / baudrate)-1) << 1)
-#endif
- | CPM_BRG_EN;
+ ((((cpu_clock/16) / baudrate)-1) << 1) | CPM_BRG_EN;
}
void
/*
* Measure CPU clock speed (core clock GCLK1, GCLK2)
+ *
* (Approx. GCLK frequency in Hz)
*
* Initializes timer 2 and PIT, but disables them before return.
__asm__ __volatile__(" lis 3, 0x3000
mtspr 0x3f2, 3");
}
+
+
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk (void)
+{
+#ifdef CONFIG_PPC405GP
+ PPC405_SYS_INFO sys_info;
+
+ get_sys_info(&sys_info);
+ return (sys_info.freqProcessor);
+#endif /* CONFIG_PPC405GP */
+
+#ifdef CONFIG_IOP480
+ return (66000000);
+#endif /* CONFIG_IOP480 */
+}
srwi r3, r3, 31 /* >>31 => select bit 0 */
blr
-/*
- * Delay for a number of microseconds
- * -- Use the BUS timer (assumes 66 MHz) -- FIXME --
- */
- .globl udelay
-udelay:
-#ifdef CONFIG_ADCIOP
- mulli r4,r3,66 /* 66 MHz (15ns) -> 1us = 66 * 15ns */
-#endif
-#ifdef CONFIG_PPC405GP
- mulli r4,r3,200 /* 200 MHz (5ns) -> 1us = 200 * 5ns */
-#endif
-1: mftbu r5
- mftb r6
- mftbu r7
- cmp 0,r5,r7
- bne 1b /* Get [synced] base time */
- addc r9,r6,r4 /* Compute end time */
- addze r8,r5
-2: mftbu r5
- cmp 0,r5,r8
- blt 2b
- bgt 3f
- mftb r6
- cmp 0,r6,r9
- blt 2b
-3: blr
-
-
.globl get_pvr
get_pvr:
mfspr r3, PVR
addis r3,0,ext_bus_cntlr_init@h // store the address of the
ori r3,r3,ext_bus_cntlr_init@l // ext_bus_cntlr_init functn in r3
#else
- addis r3,0,0x00fe // store the address of the
- ori r3,r3,0x24f4 // ext_bus_cntlr_init functn in r3
+ addis r3,0,0xfffd // store the address of the
+ ori r3,r3,0x24ec // ext_bus_cntlr_init functn in r3
#endif
addi r4,0,14 // set ctr to 10; used to prefetch
mtctr r4 // 10 cache lines to fit this function
projects / users / rw / ppcboot.git / commitdiff