powerpc/47x: Use the new ppc-opcode infrastructure

Don't use 47x only #defines for TLBIVAX or ICBT, supply and use helpers
in ppc-opcode.h

This fixes a compile breakage.

Signed-off-by: Tony Breeds <tony@bakeyournoodle.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 5f73ce63fcaeb79a6a10d7d77b92d82ad26331db..66bec4611cacc45704af9d781383c28c24148fd6 100644 (file)
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -86,6 +86,7 @@
 #define PPC_INST_DCBA_MASK             0xfc0007fe
 #define PPC_INST_DCBAL                 0x7c2005ec
 #define PPC_INST_DCBZL                 0x7c2007ec
+#define PPC_INST_ICBT                  0x7c00002c
 #define PPC_INST_ISEL                  0x7c00001e
 #define PPC_INST_ISEL_MASK             0xfc00003e
 #define PPC_INST_LDARX                 0x7c0000a8
@@ -198,6 +199,7 @@
 #define __PPC_MB(s)    (((s) & 0x1f) << 6)
 #define __PPC_ME(s)    (((s) & 0x1f) << 1)
 #define __PPC_BI(s)    (((s) & 0x1f) << 16)
+#define __PPC_CT(t)    (((t) & 0x0f) << 21)
 
 /*
  * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
@@ -260,6 +262,8 @@
                                        __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
 #define PPC_SLBFEE_DOT(t, b)   stringify_in_c(.long PPC_INST_SLBFEE | \
                                        __PPC_RT(t) | __PPC_RB(b))
+#define PPC_ICBT(c,a,b)                stringify_in_c(.long PPC_INST_ICBT | \
+                                      __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
 /* PASemi instructions */
 #define LBZCIX(t,a,b)          stringify_in_c(.long PPC_INST_LBZCIX | \
                                       __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))

diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index fab919fd1384b8d3a8f589bc368f0e4bdaf03903..626ad081639f0e25e910bd3207082d097a684c6c 100644 (file)
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -190,12 +190,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
 
 #ifdef CONFIG_PPC_47x
 
-/*
- * 47x variant of icbt
- */
-# define ICBT(CT,RA,RB)        \
-       .long   0x7c00002c | ((CT) << 21) | ((RA) << 16) | ((RB) << 11)
-
 /*
  * _tlbivax_bcast is only on 47x. We don't bother doing a runtime
  * check though, it will blow up soon enough if we mistakenly try
@@ -208,8 +202,7 @@ _GLOBAL(_tlbivax_bcast)
        wrteei  0
        mtspr   SPRN_MMUCR,r5
        isync
-/*     tlbivax 0,r3 - use .long to avoid binutils deps */
-       .long 0x7c000624 | (r3 << 11)
+       PPC_TLBIVAX(0, R3)
        isync
        eieio
        tlbsync
@@ -227,11 +220,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_476_DD2)
        bl      2f
 2:     mflr    r6
        li      r7,32
-       ICBT(0,r6,r7)           /* touch next cache line */
+       PPC_ICBT(0,R6,R7)               /* touch next cache line */
        add     r6,r6,r7
-       ICBT(0,r6,r7)           /* touch next cache line */
+       PPC_ICBT(0,R6,R7)               /* touch next cache line */
        add     r6,r6,r7
-       ICBT(0,r6,r7)           /* touch next cache line */
+       PPC_ICBT(0,R6,R7)               /* touch next cache line */
        sync
        nop
        nop