ARM: socfpga: dts: add "altr,modrst-offset" property

The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
index 32c1c8bfd5dc55ea813275bf71c5b96699bf279b..98c9f560e5c5bf633b799500cfe36272d0a564e3 100644 (file)
--- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt
+++ b/Documentation/devicetree/bindings/reset/socfpga-reset.txt
@@ -3,6 +3,7 @@ Altera SOCFPGA Reset Manager
 Required properties:
 - compatible : "altr,rst-mgr"
 - reg : Should contain 1 register ranges(address and length)
+- altr,modrst-offset : Should contain the offset of the first modrst register.
 - #reset-cells: 1
 
 Example:
@@ -10,4 +11,5 @@ Example:
                #reset-cells = <1>;
                compatible = "altr,rst-mgr";
                reg = <0xffd05000 0x1000>;
+               altr,modrst-offset = <0x10>;
        };

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 80f924deed37457409fff03e7924894ead9e4601..ed185b92bcbe101122ee3f04340c62d884a976ff 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -752,6 +752,7 @@
                        #reset-cells = <1>;
                        compatible = "altr,rst-mgr";
                        reg = <0xffd05000 0x1000>;
+                       altr,modrst-offset = <0x10>;
                };
 
                usbphy0: usbphy@0 {

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 4779b07310df81aaad4f3e87d12b1a269ef65f79..1d341dc3e598ac11ac9e54be23fbf2d094843d98 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -588,6 +588,7 @@
                        #reset-cells = <1>;
                        compatible = "altr,rst-mgr";
                        reg = <0xffd05000 0x100>;
+                       altr,modrst-offset = <0x20>;
                };
 
                scu: snoop-control-unit@ffffc000 {