[ARM] Enable VFP to be built when non-VFP capable CPUs are selected

Since we pass flags to the compiler to control code generation based
on the least capable selected CPU, if we want to include VFP support,
we must tweak the assembler flags to allow the VFP instructions.
Moreover, we must not use the mrrc/mcrr versions since these will not
be recognised by the assembler.

We do not convert all instructions to the VFP-equivalent (yet) since
binutils appears to barf on "fmrx rn, fpinst" and doesn't provide any
other way (other than using the mrc equivalent) to encode this
instruction - which is rather a problem when you have a VFP
implementation which requires these instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile
index afabac31dd1d0d14ce652cdcebe1f7a13973ef21..7e136e77971a15362bb9f3c35a98d5a3ec8865dd 100644 (file)
--- a/arch/arm/vfp/Makefile
+++ b/arch/arm/vfp/Makefile
@@ -7,6 +7,9 @@
 # EXTRA_CFLAGS := -DDEBUG
 # EXTRA_AFLAGS := -DDEBUG
 
+AFLAGS         :=$(AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp)
+LDFLAGS                +=--no-warn-mismatch
+
 obj-y                  += vfp.o
 
-vfp-$(CONFIG_VFP)      += entry.o vfpmodule.o vfphw.o vfpsingle.o vfpdouble.o
+vfp-$(CONFIG_VFP)      += vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o

diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index a3f65b47aea9edfdbfe7c88fe303ca41c15fbf3b..eb683cd77163d0b4d4c3e55fe44b213d241a9d7d 100644 (file)
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -192,7 +192,7 @@ vfp_get_double:
        add     pc, pc, r0, lsl #3
        mov     r0, r0
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-       mrrc    p11, 1, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
+       fmrrd   r0, r1, d\dr
        mov     pc, lr
        .endr
 
@@ -206,6 +206,6 @@ vfp_put_double:
        add     pc, pc, r0, lsl #3
        mov     r0, r0
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-       mcrr    p11, 1, r1, r2, c\dr    @ fmdrr r1, r2, d\dr
+       fmdrr   d\dr, r1, r2
        mov     pc, lr
        .endr