arm64: dts: freescale: imx93-phyboard-segin: Add RTC support

Add support for RTC connected via I2C on phyBOARD-Segin-i.MX93. Set
default RTC by configuring the aliases.

Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index 525f52789f8b7f84335871097168f76fa8622d3d..38b89398e646d9141018ea4f3901b95b5a3d633a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -17,6 +17,11 @@
        compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
                     "fsl,imx93";
 
+       aliases {
+               rtc0 = &i2c_rtc;
+               rtc1 = &bbnsm_rtc;
+       };
+
        chosen {
                stdout-path = &lpuart1;
        };
@@ -33,6 +38,24 @@
        };
 };
 
+/* I2C2 */
+&lpi2c2 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpi2c2>;
+       status = "okay";
+
+       /* RTC */
+       i2c_rtc: rtc@68 {
+               compatible = "microcrystal,rv4162";
+               reg = <0x68>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_rtc>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
 /* Console */
 &lpuart1 {
        pinctrl-names = "default";
@@ -56,6 +79,13 @@
 };
 
 &iomuxc {
+       pinctrl_lpi2c2: lpi2c2grp {
+               fsl,pins = <
+                       MX93_PAD_I2C2_SCL__LPI2C2_SCL           0x40000b9e
+                       MX93_PAD_I2C2_SDA__LPI2C2_SDA           0x40000b9e
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX93_PAD_UART1_RXD__LPUART1_RX          0x31e
@@ -69,6 +99,12 @@
                >;
        };
 
+       pinctrl_rtc: rtcgrp {
+               fsl,pins = <
+                       MX93_PAD_ENET2_RD2__GPIO4_IO26          0x31e
+               >;
+       };
+
        pinctrl_usdhc2_cd: usdhc2cdgrp {
                fsl,pins = <
                        MX93_PAD_SD2_CD_B__GPIO3_IO00           0x31e