arm64: dts: renesas: Add initial device tree for RZ/V2N EVK

Add the initial device tree for the Renesas RZ/V2N EVK board, based on
the R9A09G056N48 SoC. Enable basic board functionality, including:
  - Memory mapping (reserve the first 128MB for the secure area)
  - Clock inputs (QEXTAL, RTXIN, AUDIO_EXTAL)
  - PINCTRL configurations for peripherals
  - Serial console (SCIF)
  - SDHI1 with power control and UHS modes

Update the Makefile to include the new DTB.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-13-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index d25e665ee4bfb98f4d0e71cd5d05c6ba709a6ef6..d8a8d7ca4c58abd002d619d26a1c020349e5863b 100644 (file)
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -152,6 +152,8 @@ dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
 
+dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb
+
 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
 

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
new file mode 100644 (file)
index 0000000..24343fc
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2N EVK board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "r9a09g056.dtsi"
+
+/ {
+       model = "Renesas RZ/V2N EVK Board based on r9a09g056n48";
+       compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056";
+
+       aliases {
+               mmc1 = &sdhi1;
+               serial0 = &scif;
+       };
+
+       chosen {
+               bootargs = "ignore_loglevel";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@48000000 {
+               device_type = "memory";
+               /* first 128MB is reserved for secure area. */
+               reg = <0x0 0x48000000 0x1 0xf8000000>;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       vqmmc_sdhi1: regulator-vqmmc-sdhi1 {
+               compatible = "regulator-gpio";
+               regulator-name = "SDHI1 VqmmC";
+               gpios = <&pinctrl RZV2N_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+               gpios-states = <0>;
+               states = <3300000 0>, <1800000 1>;
+       };
+};
+
+&audio_extal_clk {
+       clock-frequency = <22579200>;
+};
+
+&pinctrl {
+       scif_pins: scif {
+               pins = "SCIF_TXD", "SCIF_RXD";
+               renesas,output-impedance = <1>;
+       };
+
+       sd1-pwr-en-hog {
+               gpio-hog;
+               gpios = <RZV2N_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+               output-high;
+               line-name = "sd1_pwr_en";
+       };
+
+       sdhi1_pins: sd1 {
+               sd1-cd {
+                       pinmux = <RZV2N_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
+               };
+
+               sd1-clk {
+                       pins = "SD1CLK";
+                       renesas,output-impedance = <3>;
+                       slew-rate = <0>;
+               };
+
+               sd1-dat-cmd {
+                       pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD";
+                       input-enable;
+                       renesas,output-impedance = <3>;
+                       slew-rate = <0>;
+               };
+       };
+};
+
+&qextal_clk {
+       clock-frequency = <24000000>;
+};
+
+&rtxin_clk {
+       clock-frequency = <32768>;
+};
+
+&scif {
+       pinctrl-0 = <&scif_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&sdhi1 {
+       pinctrl-0 = <&sdhi1_pins>;
+       pinctrl-1 = <&sdhi1_pins>;
+       pinctrl-names = "default", "state_uhs";
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&vqmmc_sdhi1>;
+       bus-width = <4>;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       status = "okay";
+};