drm/amd/display: Waiting for 1 frame to fix the flash issue on PSR1

[Why]
Needs more frames waiting before the PSR_Exit sending for the specific
TCON.

[How]
Add relock_delay_frame_cnt to control how many frames waiting are needed
before the PSR_Exit sending. The default value is 0. The Driver side can
set this variable for specific TCONs.

Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Ryan Lin <tsung-hua.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index cda1592c3a5be32038263d1fa90d52c3dc05497b..2d3201b77d6a0d66eb0f88221fbe19c2e429c8f0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -413,6 +413,11 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
        else
                copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0;
 
+       //WA for PSR1 on specific TCON, require frame delay for frame re-lock
+       copy_settings_data->relock_delay_frame_cnt = 0;
+       if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
+               copy_settings_data->relock_delay_frame_cnt = 2;
+
        dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
        dc_dmub_srv_cmd_execute(dc->dmub_srv);
        dc_dmub_srv_wait_idle(dc->dmub_srv);

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 9df330c86a55b991da0f9519316f8a708516cfe8..34b03bc7f8382f6dddeba5c64ce7aceef19abca7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1876,10 +1876,14 @@ struct dmub_cmd_psr_copy_settings_data {
         * Use FSM state for PSR power up/down
         */
        uint8_t use_phy_fsm;
+       /**
+        * frame delay for frame re-lock
+        */
+       uint8_t relock_delay_frame_cnt;
        /**
         * Explicit padding to 2 byte boundary.
         */
-       uint8_t pad3[2];
+       uint8_t pad3;
 };
 
 /**