}
 #endif
 
-static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
+static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
+                                unsigned long trigger)
 {
        struct irq_chip *chip = &ioapic_chip;
        irq_flow_handler_t hdl;
                fasteoi = false;
        }
 
-       if (irq_remapped(irq_get_chip_data(irq))) {
+       if (irq_remapped(cfg)) {
                irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
                chip = &ir_ioapic_chip;
                fasteoi = trigger != 0;
                return;
        }
 
-       ioapic_register_intr(irq, trigger);
+       ioapic_register_intr(irq, cfg, trigger);
        if (irq < legacy_pic->nr_legacy_irqs)
                legacy_pic->mask(irq);
 
 
        dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
 
-       if (irq_remapped(irq_get_chip_data(irq))) {
+       if (irq_remapped(cfg)) {
                struct irte irte;
                int ir_index;
                u16 sub_handle;