}
 }
 
-void hsw_enable_ips(struct intel_crtc *crtc)
+void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
 {
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
 
        }
 }
 
-void hsw_disable_ips(struct intel_crtc *crtc)
+void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
 {
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
 
-       if (!crtc->config->ips_enabled)
+       if (!crtc_state->ips_enabled)
                return;
 
        assert_plane_enabled(dev_priv, crtc->plane);
  * completely hide the primary plane.
  */
 static void
-intel_post_enable_primary(struct drm_crtc *crtc)
+intel_post_enable_primary(struct drm_crtc *crtc,
+                         const struct intel_crtc_state *new_crtc_state)
 {
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
         * when going from primary only to sprite only and vice
         * versa.
         */
-       hsw_enable_ips(intel_crtc);
+       hsw_enable_ips(new_crtc_state);
 
        /*
         * Gen2 reports pipe underruns whenever all planes are disabled.
 
 /* FIXME move all this to pre_plane_update() with proper state tracking */
 static void
-intel_pre_disable_primary(struct drm_crtc *crtc)
+intel_pre_disable_primary(struct drm_crtc *crtc,
+                         const struct intel_crtc_state *old_crtc_state)
 {
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
         * when going from primary only to sprite only and vice
         * versa.
         */
-       hsw_disable_ips(intel_crtc);
+       hsw_disable_ips(old_crtc_state);
 }
 
 /* FIXME get rid of this and use pre_plane_update */
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
 
-       intel_pre_disable_primary(crtc);
+       intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state));
 
        /*
         * Vblank time updates from the shadow to live plane control register
                if (primary_state->base.visible &&
                    (needs_modeset(&pipe_config->base) ||
                     !old_primary_state->base.visible))
-                       intel_post_enable_primary(&crtc->base);
+                       intel_post_enable_primary(&crtc->base, pipe_config);
        }
 }
 
 
                if (old_primary_state->base.visible &&
                    (modeset || !primary_state->base.visible))
-                       intel_pre_disable_primary(&crtc->base);
+                       intel_pre_disable_primary(&crtc->base, old_crtc_state);
        }
 
        /*
 
 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
 
 bool intel_crtc_active(struct intel_crtc *crtc);
-void hsw_enable_ips(struct intel_crtc *crtc);
-void hsw_disable_ips(struct intel_crtc *crtc);
+void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
+void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
                                 struct intel_crtc_state *pipe_config);