#define SUN4V_CHIP_NIAGARA5 0x05
#define SUN4V_CHIP_SPARC_M6 0x06
#define SUN4V_CHIP_SPARC_M7 0x07
-#define SUN4V_CHIP_SPARC_SN 0x08
+#define SUN4V_CHIP_SPARC_M8 0X08
+#define SUN4V_CHIP_SPARC_SN 0x7a
#define SUN4V_CHIP_SPARC64X 0x8a
#define SUN4V_CHIP_UNKNOWN 0xff
sparc_pmu_type = "sparc-m7";
break;
+ case SUN4V_CHIP_SPARC_M8:
+ sparc_cpu_type = "SPARC-M8";
+ sparc_fpu_type = "SPARC-M8 integrated FPU";
+ sparc_pmu_type = "sparc-m8";
+
case SUN4V_CHIP_SPARC_SN:
sparc_cpu_type = "SPARC-SN (Sonoma)";
sparc_fpu_type = "SPARC-SN integrated FPU";
cmp %g2, '7'
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_M7, %g4
+ cmp %g2, '8'
+ be,pt %xcc, 5f
+ mov SUN4V_CHIP_SPARC_M8, %g4
cmp %g2, 'N'
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_SN, %g4