net: mvpp2: force the XLG MAC link up or down when not using in-band

This patch force the XLG MAC link state in the phylink link_up() and
link_down() helpers when not using in-band auto-negotiation. This mimics
what's already done for the GMAC and follows what's advised in the
phylink documentation.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 687e011de5ef6169486959172457ba5536d74a99..c9edeac9ec01c2a1261ef2aecd98576ef911156a 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -430,6 +430,8 @@
 #define MVPP22_XLG_CTRL0_REG                   0x100
 #define     MVPP22_XLG_CTRL0_PORT_EN           BIT(0)
 #define     MVPP22_XLG_CTRL0_MAC_RESET_DIS     BIT(1)
+#define     MVPP22_XLG_CTRL0_FORCE_LINK_DOWN   BIT(2)
+#define     MVPP22_XLG_CTRL0_FORCE_LINK_PASS   BIT(3)
 #define     MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN   BIT(7)
 #define     MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN   BIT(8)
 #define     MVPP22_XLG_CTRL0_MIB_CNT_DIS       BIT(14)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index b1add5c6b75c3b54127ee908a83bf03c3e4233d2..ba40b06d3ca39f1d9859c9c01118e9c550d5d863 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -4684,6 +4684,7 @@ static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
 
        /* Make sure the port is disabled when reconfiguring the mode */
        mvpp2_port_disable(port);
+
        if (port->priv->hw_version == MVPP22 && change_interface) {
                mvpp22_gop_mask_irq(port);
 
@@ -4717,11 +4718,18 @@ static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
        struct mvpp2_port *port = netdev_priv(dev);
        u32 val;
 
-       if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) {
-               val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
-               val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
-               val |= MVPP2_GMAC_FORCE_LINK_PASS;
-               writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+       if (!phylink_autoneg_inband(mode)) {
+               if (mvpp2_is_xlg(interface)) {
+                       val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+                       val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
+                       val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
+                       writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+               } else {
+                       val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+                       val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
+                       val |= MVPP2_GMAC_FORCE_LINK_PASS;
+                       writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+               }
        }
 
        mvpp2_port_enable(port);
@@ -4737,11 +4745,18 @@ static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
        struct mvpp2_port *port = netdev_priv(dev);
        u32 val;
 
-       if (!phylink_autoneg_inband(mode) && !mvpp2_is_xlg(interface)) {
-               val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
-               val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
-               val |= MVPP2_GMAC_FORCE_LINK_DOWN;
-               writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+       if (!phylink_autoneg_inband(mode)) {
+               if (mvpp2_is_xlg(interface)) {
+                       val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+                       val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
+                       val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
+                       writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+               } else {
+                       val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+                       val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
+                       val |= MVPP2_GMAC_FORCE_LINK_DOWN;
+                       writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+               }
        }
 
        netif_tx_stop_all_queues(dev);