ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \
        amdgpu_amdkfd_gfx_v7.o
 
-amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o
+amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
 
 amdgpu-y += \
        vi.o
 
 #include "amdgpu_pm.h"
 #include <drm/amdgpu_drm.h>
 #include "amdgpu_powerplay.h"
+#include "si_dpm.h"
 #include "cik_dpm.h"
 #include "vi_dpm.h"
 
                amd_pp->pp_handle = (void *)adev;
 
                switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+               case CHIP_TAHITI:
+               case CHIP_PITCAIRN:
+               case CHIP_VERDE:
+               case CHIP_OLAND:
+               case CHIP_HAINAN:
+                       amd_pp->ip_funcs = &si_dpm_ip_funcs;
+               break;
+#endif
 #ifdef CONFIG_DRM_AMDGPU_CIK
                case CHIP_BONAIRE:
                case CHIP_HAWAII:
 
 
        return reference_clock;
 }
+
 //xxx:not implemented
 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 {
                .rev = 0,
                .funcs = &si_ih_ip_funcs,
        },
-/*     {
+       {
                .type = AMD_IP_BLOCK_TYPE_SMC,
                .major = 6,
                .minor = 0,
                .rev = 0,
-               .funcs = &si_null_ip_funcs,
+               .funcs = &amdgpu_pp_ip_funcs,
        },
-       */
        {
                .type = AMD_IP_BLOCK_TYPE_DCE,
                .major = 6,
                .major = 6,
                .minor = 0,
                .rev = 0,
-               .funcs = &si_null_ip_funcs,
+               .funcs = &amdgpu_pp_ip_funcs,
        },
        {
                .type = AMD_IP_BLOCK_TYPE_GFX,