}
 }
 
+static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
+                                                   u32 reg, u32 *val)
+{
+       return -EINVAL;
+}
 
 /* helper to disable agp */
 /**
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &r100_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r100_pci_gart_tlb_flush,
                .get_page_entry = &r100_pci_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &r100_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r100_pci_gart_tlb_flush,
                .get_page_entry = &r100_pci_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &r300_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r100_pci_gart_tlb_flush,
                .get_page_entry = &r100_pci_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &r300_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &rv370_pcie_gart_tlb_flush,
                .get_page_entry = &rv370_pcie_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &r300_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &rv370_pcie_gart_tlb_flush,
                .get_page_entry = &rv370_pcie_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &rs400_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &rs400_gart_tlb_flush,
                .get_page_entry = &rs400_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &rs600_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &rs600_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &rs690_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &rs400_gart_tlb_flush,
                .get_page_entry = &rs400_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &rv515_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &rv370_pcie_gart_tlb_flush,
                .get_page_entry = &rv370_pcie_gart_get_page_entry,
        .mmio_hdp_flush = NULL,
        .gui_idle = &r100_gui_idle,
        .mc_wait_for_idle = &r520_mc_wait_for_idle,
+       .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
        .gart = {
                .tlb_flush = &rv370_pcie_gart_tlb_flush,
                .get_page_entry = &rv370_pcie_gart_get_page_entry,