return nvme_wait_ready(dev, cap, true);
 }
 
+static int nvme_shutdown_ctrl(struct nvme_dev *dev)
+{
+       unsigned long timeout;
+       u32 cc;
+
+       cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
+       writel(cc, &dev->bar->cc);
+
+       timeout = 2 * HZ + jiffies;
+       while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
+                                                       NVME_CSTS_SHST_CMPLT) {
+               msleep(100);
+               if (fatal_signal_pending(current))
+                       return -EINTR;
+               if (time_after(jiffies, timeout)) {
+                       dev_err(&dev->pci_dev->dev,
+                               "Device shutdown incomplete; abort shutdown\n");
+                       return -ENODEV;
+               }
+       }
+
+       return 0;
+}
+
 static int nvme_configure_admin_queue(struct nvme_dev *dev)
 {
        int result;
        list_del_init(&dev->node);
        spin_unlock(&dev_list_lock);
 
+       if (dev->bar)
+               nvme_shutdown_ctrl(dev);
        nvme_dev_unmap(dev);
 }
 
 
        NVME_CC_SHN_NONE        = 0 << 14,
        NVME_CC_SHN_NORMAL      = 1 << 14,
        NVME_CC_SHN_ABRUPT      = 2 << 14,
+       NVME_CC_SHN_MASK        = 3 << 14,
        NVME_CC_IOSQES          = 6 << 16,
        NVME_CC_IOCQES          = 4 << 20,
        NVME_CSTS_RDY           = 1 << 0,
        NVME_CSTS_SHST_NORMAL   = 0 << 2,
        NVME_CSTS_SHST_OCCUR    = 1 << 2,
        NVME_CSTS_SHST_CMPLT    = 2 << 2,
+       NVME_CSTS_SHST_MASK     = 3 << 2,
 };
 
 #define NVME_VS(major, minor)  (major << 16 | minor)