/* KMS EnterVT equivalent */
        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+               if (HAS_PCH_SPLIT(dev))
+                       ironlake_init_pch_refclk(dev);
+
                mutex_lock(&dev->struct_mutex);
                dev_priv->mm.suspended = 0;
 
                error = i915_gem_init_hw(dev);
                mutex_unlock(&dev->struct_mutex);
 
-               if (HAS_PCH_SPLIT(dev))
-                       ironlake_init_pch_refclk(dev);
-
+               intel_modeset_init_hw(dev);
                drm_mode_config_reset(dev);
                drm_irq_install(dev);
 
                mutex_lock(&dev->mode_config.mutex);
                drm_helper_resume_force_mode(dev);
                mutex_unlock(&dev->mode_config.mutex);
-
-               if (IS_IRONLAKE_M(dev))
-                       ironlake_enable_rc6(dev);
        }
 
        intel_opregion_init(dev);
 
                I915_WRITE(IER, dev_priv->saveIER);
                I915_WRITE(IMR, dev_priv->saveIMR);
        }
-       mutex_unlock(&dev->struct_mutex);
-
-       if (drm_core_check_feature(dev, DRIVER_MODESET))
-               intel_modeset_init_hw(dev);
-
-       mutex_lock(&dev->struct_mutex);
 
        /* Cache mode state */
        I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 
 
        if (IS_IRONLAKE_M(dev)) {
                ironlake_enable_drps(dev);
+               ironlake_enable_rc6(dev);
                intel_init_emon(dev);
        }
 
        i915_disable_vga(dev);
        intel_setup_outputs(dev);
 
-       intel_modeset_init_hw(dev);
-
        INIT_WORK(&dev_priv->idle_work, intel_idle_update);
        setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
                    (unsigned long)dev);
 
 void intel_modeset_gem_init(struct drm_device *dev)
 {
-       if (IS_IRONLAKE_M(dev))
-               ironlake_enable_rc6(dev);
+       intel_modeset_init_hw(dev);
 
        intel_setup_overlay(dev);
 }