rtw89: reset BA CAM

BA CAM is used to react receiving AMPDU packets, so reset them to be
expected initial state.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220408001353.17188-7-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c
index b60b9255e3fa251d895dd79b4ee0d4d4ba719495..ba8c7d3e176cc93d2d1608ba32090247a114e9a2 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/mac.c
+++ b/drivers/net/wireless/realtek/rtw89/mac.c
@@ -1964,6 +1964,21 @@ static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
        return 0;
 }
 
+static void rst_bacam(struct rtw89_dev *rtwdev)
+{
+       u32 val32;
+       int ret;
+
+       rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK,
+                          S_AX_BACAM_RST_ALL);
+
+       ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0,
+                                      1, 1000, false,
+                                      rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK);
+       if (ret)
+               rtw89_warn(rtwdev, "failed to reset BA CAM\n");
+}
+
 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
 {
 #define TRXCFG_RMAC_CCA_TO     32
@@ -1978,6 +1993,9 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
        if (ret)
                return ret;
 
+       if (mac_idx == RTW89_MAC_0)
+               rst_bacam(rtwdev);
+
        reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx);
        rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);
 

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index e5f8374f49ad530d9801440602e115c5e1a90bda..bc343e756aad72dc700f922dcf0a23ad3ef7a7db 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -2819,6 +2819,8 @@
 #define R_AX_RESPBA_CAM_CTRL 0xCE3C
 #define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C
 #define B_AX_SSN_SEL BIT(2)
+#define B_AX_BACAM_RST_MASK GENMASK(1, 0)
+#define S_AX_BACAM_RST_ALL 2
 
 #define R_AX_PPDU_STAT 0xCE40
 #define R_AX_PPDU_STAT_C1 0xEE40