drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7

not update the dpm table with user's setting

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 6c99cbf51c08fd035fa3da585c06b8b7074bdb29..ed35ec0341e671ab8f5cee4d89d2417283147bf3 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3588,9 +3588,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
                        break;
        }
 
-       if (i >= sclk_table->count)
+       if (i >= sclk_table->count) {
                data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
-       else {
+               sclk_table->dpm_levels[i-1].value = sclk;
+       } else {
        /* TODO: Check SCLK in DAL's minimum clocks
         * in case DeepSleep divider update is required.
         */
@@ -3605,9 +3606,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
                        break;
        }
 
-       if (i >= mclk_table->count)
+       if (i >= mclk_table->count) {
                data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
-
+               mclk_table->dpm_levels[i-1].value = mclk;
+       }
 
        if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
                data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;