#define DDRC_V2_EVENT_TYPE     0xe74
 #define DDRC_V2_PERF_CTRL      0xeA0
 
+/* DDRC interrupt registers definition in v3 */
+#define DDRC_V3_INT_MASK       0x534
+#define DDRC_V3_INT_STATUS     0x538
+#define DDRC_V3_INT_CLEAR      0x53C
+
 /* DDRC has 8-counters */
 #define DDRC_NR_COUNTERS       0x8
 #define DDRC_V1_PERF_CTRL_EN   0x2
        .private = &hisi_ddrc_v2_pmu_regs,
 };
 
+static struct hisi_ddrc_pmu_regs hisi_ddrc_v3_pmu_regs = {
+       .event_cnt = DDRC_V2_EVENT_CNT,
+       .event_ctrl = DDRC_V2_EVENT_CTRL,
+       .event_type = DDRC_V2_EVENT_TYPE,
+       .perf_ctrl = DDRC_V2_PERF_CTRL,
+       .perf_ctrl_en = DDRC_V2_PERF_CTRL_EN,
+       .int_mask = DDRC_V3_INT_MASK,
+       .int_clear = DDRC_V3_INT_CLEAR,
+       .int_status = DDRC_V3_INT_STATUS,
+};
+
+static const struct hisi_pmu_dev_info hisi_ddrc_v3 = {
+       .counter_bits = 48,
+       .check_event = DDRC_V2_NR_EVENTS,
+       .attr_groups = hisi_ddrc_pmu_v2_attr_groups,
+       .private = &hisi_ddrc_v3_pmu_regs,
+};
+
 static const struct acpi_device_id hisi_ddrc_pmu_acpi_match[] = {
        { "HISI0233", (kernel_ulong_t)&hisi_ddrc_v1 },
        { "HISI0234", (kernel_ulong_t)&hisi_ddrc_v2 },
+       { "HISI0235", (kernel_ulong_t)&hisi_ddrc_v3 },
        {}
 };
 MODULE_DEVICE_TABLE(acpi, hisi_ddrc_pmu_acpi_match);